| Message ID | 20231005155618.700312-1-peter.griffin@linaro.org |
|---|---|
| Headers | show |
| Series | Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board | expand |
On 05/10/2023 17:55, Peter Griffin wrote: > Add the gs101 SoC interrupt header that provides human readable > constants for all the IRQs in the SoC. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++++++++++++++ > 1 file changed, 758 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/gs101.h > > diff --git a/include/dt-bindings/interrupt-controller/gs101.h b/include/dt-bindings/interrupt-controller/gs101.h > new file mode 100644 > index 000000000000..51c8eb54eca2 > --- /dev/null > +++ b/include/dt-bindings/interrupt-controller/gs101.h > @@ -0,0 +1,758 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * This header provides constants for gs101 interrupt controller. > + * > + * Copyright 2019-2023 Google LLC > + * > + */ > + > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS101_H > + > +#define ITNO IRQ_TYPE_NONE > +#define ITER IRQ_TYPE_EDGE_RISING > +#define ITEF IRQ_TYPE_EDGE_FALLING > +#define ITEB IRQ_TYPE_EDGE_BOTH > +#define ITLH IRQ_TYPE_LEVEL_HIGH > +#define ITLL IRQ_TYPE_LEVEL_LOW No, these are not bindings. > + > +#define IRQ_ALIVE_EINT0 0 > +#define IRQ_ALIVE_EINT1 1 We do not keep interrupt numbers as bindings. Please drop entire file. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Provide dt-schema documentation for Google gs101 SoC clock controller. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../bindings/clock/google,gs101-clock.yaml | 109 ++++++++++++++++++ > 1 file changed, 109 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > new file mode 100644 > index 000000000000..a28d05d88afe > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml > @@ -0,0 +1,109 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Google GS101 SoC clock controller > + > +maintainers: > + - Peter Griffin <peter.griffin@linaro.org> > + > +description: | > + Google GS101 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. The root clock in that clock tree > + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate > + clock in dts. > + > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. > + > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All clocks available for usage > + in clock consumer nodes are defined as preprocessor macros in > + 'dt-bindings/clock/gs101.h' header. > + > +properties: > + compatible: > + enum: > + - google,gs101-cmu-top > + - google,gs101-cmu-apm > + - google,gs101-cmu-misc > + > + clocks: > + minItems: 1 > + maxItems: 5 I see max 2 clocks. > + > + clock-names: > + minItems: 1 > + maxItems: 5 > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: google,gs101-cmu-top > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (24.576 MHz) > + > + clock-names: > + items: > + - const: oscclk > + > + - if: > + properties: > + compatible: > + contains: > + const: google,gs101-cmu-misc > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (24.576 MHz) > + - description: Misc bus clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: dout_cmu_misc_bus What about google,gs101-cmu-apm? > + > +required: "required:" go before "allOf:" > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + - reg > + > +additionalProperties: false > + > +examples: > + # Clock controller node for CMU_TOP > + - | > + #include <dt-bindings/interrupt-controller/gs101.h> > + soc { > + #address-cells = <2>; > + #size-cells = <1>; Messed indentation. > + > +... Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Add the "google,gs101-pinctrl" compatible to the dt-schema bindings > documentation. > > Add maxItems of 50 for the interrupts property as gs101 can have > multiple irqs. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml > index 26614621774a..e0f37f8ae8e7 100644 > --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml > @@ -54,11 +54,13 @@ properties: > - samsung,exynos850-pinctrl > - samsung,exynosautov9-pinctrl > - tesla,fsd-pinctrl > + - google,gs101-pinctrl Alphanumerical order > > interrupts: > description: > Required for GPIO banks supporting external GPIO interrupts. > - maxItems: 1 > + minItems: 1 > + maxItems: 50 You need to add to allOf: a new "if:then:else:" which will: 1. narrow this for Google (with some description - is it interrupt per GPIO? per bank?) 2. else: maxItems: 1 Best regards, Krzysztof
On 10/05/2023, Peter Griffin wrote: > Add the "google,gs101-wdt" and "google,gs201-wdt" compatibles to the > dt-schema documentation. > > gs101 SoC has two CPU clusters and each cluster has its own dedicated > watchdog timer (similar to exynos850 and exynosautov9 SoCs). > > These WDT instances are controlled using different bits in PMU > registers. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../devicetree/bindings/watchdog/samsung-wdt.yaml | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > index 8fb6656ba0c2..30f5949037fc 100644 > --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml > @@ -24,6 +24,8 @@ properties: > - samsung,exynos7-wdt # for Exynos7 > - samsung,exynos850-wdt # for Exynos850 > - samsung,exynosautov9-wdt # for Exynosautov9 > + - google,gs101-wdt # for Google gs101 > + - google,gs201-wdt # for Google gs101 For "google,gs201-wdt the comment should be "for Google gs201". Regards, Will > > reg: > maxItems: 1 > @@ -42,13 +44,13 @@ properties: > samsung,cluster-index: > $ref: /schemas/types.yaml#/definitions/uint32 > description: > - Index of CPU cluster on which watchdog is running (in case of Exynos850) > + Index of CPU cluster on which watchdog is running (in case of Exynos850 or Google gsx01) > > samsung,syscon-phandle: > $ref: /schemas/types.yaml#/definitions/phandle > description: > Phandle to the PMU system controller node (in case of Exynos5250, > - Exynos5420, Exynos7 and Exynos850). > + Exynos5420, Exynos7, Exynos850 and gsx01). > > required: > - compatible > @@ -69,6 +71,8 @@ allOf: > - samsung,exynos7-wdt > - samsung,exynos850-wdt > - samsung,exynosautov9-wdt > + - google,gs101-wdt > + - google,gs201-wdt > then: > required: > - samsung,syscon-phandle > @@ -79,6 +83,8 @@ allOf: > enum: > - samsung,exynos850-wdt > - samsung,exynosautov9-wdt > + - google,gs101-wdt > + - google,gs201-wdt > then: > properties: > clocks: > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > CMU_TOP is the top level clock management unit which contains PLLs, muxes > and gates that feed the other clock management units. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/Kconfig | 9 + > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++ > 3 files changed, 1568 insertions(+) > create mode 100644 drivers/clk/samsung/clk-gs101.c > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > index 76a494e95027..4c8f173c4dec 100644 > --- a/drivers/clk/samsung/Kconfig > +++ b/drivers/clk/samsung/Kconfig > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR Is this patch out of order? ARCH_GOOGLE_TENSOR hasn't been defined at this point in the series (it's defined in 18/21). Regards, Will > > config S3C64XX_COMMON_CLK > bool "Samsung S3C64xx clock controller support" if COMPILE_TEST > @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK > help > Support for the clock controller present on the Tesla FSD SoC. > Choose Y here only if you build for this SoC. > + > +config GOOGLE_GS101_COMMON_CLK > + bool "Google gs101 clock controller support" if COMPILE_TEST > + depends on COMMON_CLK_SAMSUNG > + depends on EXYNOS_ARM64_COMMON_CLK > + help > + Support for the clock controller present on the Google gs101 SoC. > + Choose Y here only if you build for this SoC. > \ No newline at end of file > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index ebbeacabe88f..1e69b8e14324 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > new file mode 100644 > index 000000000000..4c58fcc899be > --- /dev/null > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -0,0 +1,1558 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin <peter.griffin@linaro.org> > + * > + * Common Clock Framework support for GS101. > + */ > + > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > + > +#include <dt-bindings/clock/gs101.h> > + > +#include "clk.h" > +#include "clk-exynos-arm64.h" > + > +/* NOTE: Must be equal to the last clock ID increased by one */ > +#define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1) > + > +/* ---- CMU_TOP ------------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_TOP (0x1e080000) */ > + > +#define PLL_LOCKTIME_PLL_SHARED0 0x0000 > +#define PLL_LOCKTIME_PLL_SHARED1 0x0004 > +#define PLL_LOCKTIME_PLL_SHARED2 0x0008 > +#define PLL_LOCKTIME_PLL_SHARED3 0x000c > +#define PLL_LOCKTIME_PLL_SPARE 0x0010 > +#define PLL_CON0_PLL_SHARED0 0x0100 > +#define PLL_CON1_PLL_SHARED0 0x0104 > +#define PLL_CON2_PLL_SHARED0 0x0108 > +#define PLL_CON3_PLL_SHARED0 0x010c > +#define PLL_CON4_PLL_SHARED0 0x0110 > +#define PLL_CON0_PLL_SHARED1 0x0140 > +#define PLL_CON1_PLL_SHARED1 0x0144 > +#define PLL_CON2_PLL_SHARED1 0x0148 > +#define PLL_CON3_PLL_SHARED1 0x014c > +#define PLL_CON4_PLL_SHARED1 0x0150 > +#define PLL_CON0_PLL_SHARED2 0x0180 > +#define PLL_CON1_PLL_SHARED2 0x0184 > +#define PLL_CON2_PLL_SHARED2 0x0188 > +#define PLL_CON3_PLL_SHARED2 0x018c > +#define PLL_CON4_PLL_SHARED2 0x0190 > +#define PLL_CON0_PLL_SHARED3 0x01c0 > +#define PLL_CON1_PLL_SHARED3 0x01c4 > +#define PLL_CON2_PLL_SHARED3 0x01c8 > +#define PLL_CON3_PLL_SHARED3 0x01cc > +#define PLL_CON4_PLL_SHARED3 0x01d0 > +#define PLL_CON0_PLL_SPARE 0x0200 > +#define PLL_CON1_PLL_SPARE 0x0204 > +#define PLL_CON2_PLL_SPARE 0x0208 > +#define PLL_CON3_PLL_SPARE 0x020c > +#define PLL_CON4_PLL_SPARE 0x0210 > +#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 > +#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 > +#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 > +#define CMU_HCHGEN_CLKMUX 0x0850 > +#define POWER_FAIL_DETECT_PLL 0x0864 > +#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 > +#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 > +#define EARLY_WAKEUP_APM_CTRL 0x0878 > +#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c > +#define EARLY_WAKEUP_DPU_CTRL 0x0880 > +#define EARLY_WAKEUP_CSIS_CTRL 0x0884 > +#define EARLY_WAKEUP_APM_DEST 0x0890 > +#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 > +#define EARLY_WAKEUP_DPU_DEST 0x0898 > +#define EARLY_WAKEUP_CSIS_DEST 0x089c > +#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 > +#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 > +#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 > +#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 > +#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 > +#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 > +#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 > +#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 > +#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 > +#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 > + > +#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 > +#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 > +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 > +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 > +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 > +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 > +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c > +#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 > +#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 > +#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 > +#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 > +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 > +#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c > +#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 > +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 > +#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac > +#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 > +#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 > +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc > +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 > +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc > +#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 > +#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 > +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 > +#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 > +#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 > +#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 > +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 > + > +#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 > +#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 > +#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 > +#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c > +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c > +#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 > +#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c > +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 > +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 > +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 > +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c > +#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 > +#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 > +#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 > +#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c > +#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 > +#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 > +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 > +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c > +#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 > +#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 > +#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 > +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c > +#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 > +#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 > +#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 > +#define CLK_CON_DIV_CLKCMU_HPM 0x187c > +#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 > +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 > +#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 > +#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c > +#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 > +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 > +#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 > +#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c > +#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 > +#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 > +#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 > +#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac > +#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 > +#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 > +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 > +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc > +#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 > +#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 > +#define CLK_CON_DIV_CLKCMU_OTP 0x18c8 > +#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc > +#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 > +#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 > +#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 > +#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc > +#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 > +#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 > +#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 > +#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec > +#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 > +#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 > +#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 > +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc > +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 > +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 > +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 > +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c > +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 > +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 > +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 > +#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c > +#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 > + > +/* CLK_CON_GAT_UPDATES */ > +#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 > +#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 > +#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 > +#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c > +#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 > +#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 > +#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 > +#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c > +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 > +#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 > +#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 > +#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c > +#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c > +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 > +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 > +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 > +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 > +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c > +#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 > +#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 > +#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 > +#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 > +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 > +#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c > +#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 > +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 > +#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc > +#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 > +#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 > +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc > +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 > +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 > +#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 > +#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 > +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 > +#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 > +#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 > +#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c > + > +#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c > +#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 > +#define DMYQCH_CON_OTP_QCH 0x3024 > +#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 > +#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 > +#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 > +#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 > +#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c > +#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 > +#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 > +#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 > +#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c > +#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 > +#define MIFMIRROR_QUEUE_ENTRY0 0x3e10 > +#define MIFMIRROR_QUEUE_ENTRY1 0x3e14 > +#define MIFMIRROR_QUEUE_ENTRY2 0x3e18 > +#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c > +#define MIFMIRROR_QUEUE_ENTRY4 0x3e20 > +#define MIFMIRROR_QUEUE_ENTRY5 0x3e24 > +#define MIFMIRROR_QUEUE_ENTRY6 0x3e28 > +#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c > +#define MIFMIRROR_QUEUE_BUSY 0x3e30 > +#define GENERALIO_ACD_CHANNEL_0 0x3f00 > +#define GENERALIO_ACD_CHANNEL_1 0x3f04 > +#define GENERALIO_ACD_CHANNEL_2 0x3f08 > +#define GENERALIO_ACD_CHANNEL_3 0x3f0c > +#define GENERALIO_ACD_MASK 0x3f14 > + > +static const unsigned long cmu_top_clk_regs[] __initconst = { > + PLL_LOCKTIME_PLL_SHARED0, > + PLL_LOCKTIME_PLL_SHARED1, > + PLL_LOCKTIME_PLL_SHARED2, > + PLL_LOCKTIME_PLL_SHARED3, > + PLL_LOCKTIME_PLL_SPARE, > + PLL_CON0_PLL_SHARED0, > + PLL_CON1_PLL_SHARED0, > + PLL_CON2_PLL_SHARED0, > + PLL_CON3_PLL_SHARED0, > + PLL_CON4_PLL_SHARED0, > + PLL_CON0_PLL_SHARED1, > + PLL_CON1_PLL_SHARED1, > + PLL_CON2_PLL_SHARED1, > + PLL_CON3_PLL_SHARED1, > + PLL_CON4_PLL_SHARED1, > + PLL_CON0_PLL_SHARED2, > + PLL_CON1_PLL_SHARED2, > + PLL_CON2_PLL_SHARED2, > + PLL_CON3_PLL_SHARED2, > + PLL_CON4_PLL_SHARED2, > + PLL_CON0_PLL_SHARED3, > + PLL_CON1_PLL_SHARED3, > + PLL_CON2_PLL_SHARED3, > + PLL_CON3_PLL_SHARED3, > + PLL_CON4_PLL_SHARED3, > + PLL_CON0_PLL_SPARE, > + PLL_CON1_PLL_SPARE, > + PLL_CON2_PLL_SPARE, > + PLL_CON3_PLL_SPARE, > + PLL_CON4_PLL_SPARE, > + CMU_CMU_TOP_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, > + CMU_HCHGEN_CLKMUX_CMU_BOOST, > + CMU_HCHGEN_CLKMUX_TOP_BOOST, > + CMU_HCHGEN_CLKMUX, > + POWER_FAIL_DETECT_PLL, > + EARLY_WAKEUP_FORCED_0_ENABLE, > + EARLY_WAKEUP_FORCED_1_ENABLE, > + EARLY_WAKEUP_APM_CTRL, > + EARLY_WAKEUP_CLUSTER0_CTRL, > + EARLY_WAKEUP_DPU_CTRL, > + EARLY_WAKEUP_CSIS_CTRL, > + EARLY_WAKEUP_APM_DEST, > + EARLY_WAKEUP_CLUSTER0_DEST, > + EARLY_WAKEUP_DPU_DEST, > + EARLY_WAKEUP_CSIS_DEST, > + EARLY_WAKEUP_SW_TRIG_APM, > + EARLY_WAKEUP_SW_TRIG_APM_SET, > + EARLY_WAKEUP_SW_TRIG_APM_CLEAR, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, > + EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, > + EARLY_WAKEUP_SW_TRIG_DPU, > + EARLY_WAKEUP_SW_TRIG_DPU_SET, > + EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, > + EARLY_WAKEUP_SW_TRIG_CSIS, > + EARLY_WAKEUP_SW_TRIG_CSIS_SET, > + EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, > + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, > + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, > + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, > + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, > + CLK_CON_MUX_MUX_CLKCMU_EH_BUS, > + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, > + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, > + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, > + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, > + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, > + CLK_CON_MUX_MUX_CLKCMU_HPM, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, > + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, > + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, > + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, > + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, > + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, > + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, > + CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, > + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, > + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, > + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, > + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, > + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, > + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, > + CLK_CON_MUX_MUX_CMU_CMUREF, > + CLK_CON_DIV_CLKCMU_BO_BUS, > + CLK_CON_DIV_CLKCMU_BUS0_BUS, > + CLK_CON_DIV_CLKCMU_BUS1_BUS, > + CLK_CON_DIV_CLKCMU_BUS2_BUS, > + CLK_CON_DIV_CLKCMU_CIS_CLK0, > + CLK_CON_DIV_CLKCMU_CIS_CLK1, > + CLK_CON_DIV_CLKCMU_CIS_CLK2, > + CLK_CON_DIV_CLKCMU_CIS_CLK3, > + CLK_CON_DIV_CLKCMU_CIS_CLK4, > + CLK_CON_DIV_CLKCMU_CIS_CLK5, > + CLK_CON_DIV_CLKCMU_CIS_CLK6, > + CLK_CON_DIV_CLKCMU_CIS_CLK7, > + CLK_CON_DIV_CLKCMU_CORE_BUS, > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, > + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_DIV_CLKCMU_CSIS_BUS, > + CLK_CON_DIV_CLKCMU_DISP_BUS, > + CLK_CON_DIV_CLKCMU_DNS_BUS, > + CLK_CON_DIV_CLKCMU_DPU_BUS, > + CLK_CON_DIV_CLKCMU_EH_BUS, > + CLK_CON_DIV_CLKCMU_G2D_G2D, > + CLK_CON_DIV_CLKCMU_G2D_MSCL, > + CLK_CON_DIV_CLKCMU_G3AA_G3AA, > + CLK_CON_DIV_CLKCMU_G3D_BUSD, > + CLK_CON_DIV_CLKCMU_G3D_GLB, > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, > + CLK_CON_DIV_CLKCMU_GDC_GDC0, > + CLK_CON_DIV_CLKCMU_GDC_GDC1, > + CLK_CON_DIV_CLKCMU_GDC_SCSC, > + CLK_CON_DIV_CLKCMU_HPM, > + CLK_CON_DIV_CLKCMU_HSI0_BUS, > + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, > + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, > + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_DIV_CLKCMU_HSI1_BUS, > + CLK_CON_DIV_CLKCMU_HSI1_PCIE, > + CLK_CON_DIV_CLKCMU_HSI2_BUS, > + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, > + CLK_CON_DIV_CLKCMU_HSI2_PCIE, > + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_DIV_CLKCMU_IPP_BUS, > + CLK_CON_DIV_CLKCMU_ITP_BUS, > + CLK_CON_DIV_CLKCMU_MCSC_ITSC, > + CLK_CON_DIV_CLKCMU_MCSC_MCSC, > + CLK_CON_DIV_CLKCMU_MFC_MFC, > + CLK_CON_DIV_CLKCMU_MIF_BUSP, > + CLK_CON_DIV_CLKCMU_MISC_BUS, > + CLK_CON_DIV_CLKCMU_MISC_SSS, > + CLK_CON_DIV_CLKCMU_OTP, > + CLK_CON_DIV_CLKCMU_PDP_BUS, > + CLK_CON_DIV_CLKCMU_PDP_VRA, > + CLK_CON_DIV_CLKCMU_PERIC0_BUS, > + CLK_CON_DIV_CLKCMU_PERIC0_IP, > + CLK_CON_DIV_CLKCMU_PERIC1_BUS, > + CLK_CON_DIV_CLKCMU_PERIC1_IP, > + CLK_CON_DIV_CLKCMU_TNR_BUS, > + CLK_CON_DIV_CLKCMU_TPU_BUS, > + CLK_CON_DIV_CLKCMU_TPU_TPU, > + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, > + CLK_CON_DIV_CLKCMU_TPU_UART, > + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, > + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, > + CLK_CON_DIV_PLL_SHARED0_DIV2, > + CLK_CON_DIV_PLL_SHARED0_DIV3, > + CLK_CON_DIV_PLL_SHARED0_DIV4, > + CLK_CON_DIV_PLL_SHARED0_DIV5, > + CLK_CON_DIV_PLL_SHARED1_DIV2, > + CLK_CON_DIV_PLL_SHARED1_DIV3, > + CLK_CON_DIV_PLL_SHARED1_DIV4, > + CLK_CON_DIV_PLL_SHARED2_DIV2, > + CLK_CON_DIV_PLL_SHARED3_DIV2, > + CLK_CON_GAT_CLKCMU_BUS0_BOOST, > + CLK_CON_GAT_CLKCMU_BUS1_BOOST, > + CLK_CON_GAT_CLKCMU_BUS2_BOOST, > + CLK_CON_GAT_CLKCMU_CORE_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, > + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, > + CLK_CON_GAT_CLKCMU_MIF_BOOST, > + CLK_CON_GAT_CLKCMU_MIF_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, > + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, > + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, > + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, > + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, > + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, > + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, > + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, > + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, > + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, > + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, > + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, > + CLK_CON_GAT_GATE_CLKCMU_HPM, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, > + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, > + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, > + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, > + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, > + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, > + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, > + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, > + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, > + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, > + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, > + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, > + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, > + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, > + DMYQCH_CON_CMU_TOP_CMUREF_QCH, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, > + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, > + DMYQCH_CON_OTP_QCH, > + QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY0_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY1_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY2_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY3_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY4_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY5_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY6_BLK_CMU_CMU_TOP, > + QUEUE_ENTRY7_BLK_CMU_CMU_TOP, > + MIFMIRROR_QUEUE_CTRL_REG, > + MIFMIRROR_QUEUE_ENTRY0, > + MIFMIRROR_QUEUE_ENTRY1, > + MIFMIRROR_QUEUE_ENTRY2, > + MIFMIRROR_QUEUE_ENTRY3, > + MIFMIRROR_QUEUE_ENTRY4, > + MIFMIRROR_QUEUE_ENTRY5, > + MIFMIRROR_QUEUE_ENTRY6, > + MIFMIRROR_QUEUE_ENTRY7, > + MIFMIRROR_QUEUE_BUSY, > + GENERALIO_ACD_CHANNEL_0, > + GENERALIO_ACD_CHANNEL_1, > + GENERALIO_ACD_CHANNEL_2, > + GENERALIO_ACD_CHANNEL_3, > + GENERALIO_ACD_MASK, > +}; > + > +static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { > + /* CMU_TOP_PURECLKCOMP */ > + PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > + NULL), > + PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", > + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, > + NULL), > + PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", > + PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, > + NULL), > +}; > + > +/* List of parent clocks for Muxes in CMU_TOP */ > +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; > +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; > +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; > +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; > +PNAME(mout_spare_pll_p) = { "oscclk", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS0 */ > +PNAME(mout_cmu_bus0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS1 */ > +PNAME(mout_cmu_bus1_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BUS2 */ > +PNAME(mout_cmu_bus2_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ > +PNAME(mout_cmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_EH */ > +PNAME(mout_cmu_eh_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL2 */ > +PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */ > +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */ > +PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_shared0_div2", > + "dout_shared1_div2", "fout_shared2_pll", > + "fout_shared3_pll", "dout_shared0_div3", > + "dout_shared1_div3", "fout_spare_pll" }; > + > +PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ > +PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_g3d_busd_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_g3d_glb_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ > +PNAME(mout_cmu_dpu_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DISP */ > +PNAME(mout_cmu_disp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */ > +PNAME(mout_cmu_g2d_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_g2d_mscl_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI0 */ > +PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_shared2_div2" }; > + > +PNAME(mout_cmu_hsi0_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_shared0_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI1 */ > +PNAME(mout_cmu_hsi1_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_shared2_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI2 */ > +PNAME(mout_cmu_hsi2_bus_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_shared2_div2" }; > + > +PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared0_div4", > + "dout_shared2_div2", "fout_spare_pll" }; > + > +PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CSIS */ > +PNAME(mout_cmu_csis_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PDP */ > +PNAME(mout_cmu_pdp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IPP */ > +PNAME(mout_cmu_ipp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3AA */ > +PNAME(mout_cmu_g3aa_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_ITP */ > +PNAME(mout_cmu_itp_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_DNS */ > +PNAME(mout_cmu_dns_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TNR */ > +PNAME(mout_cmu_tnr_bus_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MCSC */ > +PNAME(mout_cmu_mcsc_itsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_GDC */ > +PNAME(mout_cmu_gdc_scsc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_gdc_gdc0_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +PNAME(mout_cmu_gdc_gdc1_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFC */ > +PNAME(mout_cmu_mfc_mfc_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for DDRPHY0/1/2/3 */ > + > +PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", > + "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MIF0/1/2/3 */ > +PNAME(mout_cmu_mif_busp_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared0_div5", "fout_spare_pll" }; > + > +PNAME(mout_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4", > + "dout_shared2_div2", "dout_shared3_div2" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MISC */ > +PNAME(mout_cmu_misc_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_misc_sss_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC0 */ > +PNAME(mout_cmu_peric0_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_peric0_ip_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERIC1 */ > +PNAME(mout_cmu_peric1_bus_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > +PNAME(mout_cmu_peric1_ip_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_TPU */ > +PNAME(mout_cmu_tpu_tpu_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "fout_shared2_pll", "fout_shared3_pll", > + "dout_shared0_div3", "dout_shared1_div3", > + "dout_shared0_div4", "fout_spare_pll" }; > + > +PNAME(mout_cmu_tpu_uart_p) = { "dout_shared0_div4", "dout_shared2_div2", > + "dout_shared3_div2", "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_BO */ > +PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_shared0_div3", > + "fout_shared3_pll", "dout_shared1_div3", > + "dout_shared0_div4", "dout_shared1_div4", > + "fout_spare_pll" }; > + > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G2D */ > +PNAME(mout_cmu_g2d_p) = { "dout_shared0_div3", "fout_shared3_pll", > + "dout_shared1_div3", "dout_shared0_div4", > + "dout_shared1_div4", "dout_shared2_div2", > + "fout_spare_pll" }; > + > +/* gs101 */ > +static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { > + /* CMU_TOP_PURECLKCOMP */ > + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, > + PLL_CON0_PLL_SHARED0, 4, 1), > + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, > + PLL_CON0_PLL_SHARED1, 4, 1), > + MUX(CLK_MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, > + PLL_CON0_PLL_SHARED2, 4, 1), > + MUX(CLK_MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, > + PLL_CON0_PLL_SHARED3, 4, 1), > + MUX(CLK_MOUT_SPARE_PLL, "mout_spare_pll", mout_spare_pll_p, > + PLL_CON0_PLL_SPARE, 4, 1), > + > + /* BUS0 */ > + MUX(CLK_MOUT_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2), > + MUX(CLK_MOUT_CMU_BOOST, "mout_cmu_boost", mout_cmu_cmu_boost_p, > + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), > + > + /* BUS1 */ > + MUX(CLK_MOUT_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2), > + > + /* BUS2 */ > + MUX(CLK_MOUT_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 2), > + > + /* CORE */ > + MUX(CLK_MOUT_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), > + > + /* EH */ > + MUX(CLK_MOUT_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), > + > + /* CPUCL{0,1,2,} */ > + MUX(CLK_MOUT_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", mout_cmu_cpucl2_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0, 2), > + > + MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2), > + > + MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2), > + > + MUX(CLK_MOUT_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p, > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 2), > + > + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, > + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), > + > + /* G3D */ > + MUX(CLK_MOUT_G3D_SWITCH, "mout_cmu_g3d_switch", mout_cmu_g3d_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), > + > + MUX(CLK_MOUT_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 2), > + > + MUX(CLK_MOUT_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 2), > + /* DPU */ > + MUX(CLK_MOUT_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, > + CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 2), > + > + /* DISP */ > + MUX(CLK_MOUT_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 2), > + > + /* G2D */ > + MUX(CLK_MOUT_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, > + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2), > + > + MUX(CLK_MOUT_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, > + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), > + > + /* HSI0 */ > + MUX(CLK_MOUT_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", mout_cmu_hsi0_usb31drd_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0, 2), > + > + MUX(CLK_MOUT_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 2), > + > + MUX(CLK_MOUT_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", mout_cmu_hsi0_dpgtc_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), > + > + MUX(CLK_MOUT_HSI0_USBDPDGB, "mout_cmu_hsi0_usbdpdbg", mout_cmu_hsi0_usbdpdbg_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0, 2), > + > + /* HSI1 */ > + MUX(CLK_MOUT_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 2), > + > + MUX(CLK_MOUT_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 2), > + /* HSI2 */ > + MUX(CLK_MOUT_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 2), > + > + MUX(CLK_MOUT_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 2), > + > + MUX(CLK_MOUT_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", mout_cmu_hsi2_ufs_embd_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0, 2), > + > + MUX(CLK_MOUT_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", mout_cmu_hsi2_mmc_card_p, > + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0, 2), > + > + /* CSIS */ > + MUX(CLK_MOUT_CSIS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2), > + > + /* PDP */ > + MUX(CLK_MOUT_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 2), > + > + /* IPP */ > + MUX(CLK_MOUT_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 2), > + > + /* G3AA */ > + MUX(CLK_MOUT_G3AA, "mout_cmu_g3aa", mout_cmu_g3aa_p, > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 2), > + > + /* ITP */ > + MUX(CLK_MOUT_ITP, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 2), > + > + /* DNS */ > + MUX(CLK_MOUT_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 2), > + > + /* TNR */ > + MUX(CLK_MOUT_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 2), > + > + /* MCSC*/ > + MUX(CLK_MOUT_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 2), > + > + MUX(CLK_MOUT_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, > + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 2), > + > + /* GDC */ > + MUX(CLK_MOUT_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 2), > + > + MUX(CLK_MOUT_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 2), > + > + MUX(CLK_MOUT_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, > + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 2), > + > + /* MFC */ > + MUX(CLK_MOUT_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, > + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2), > + > + /* DDRPHY0/1/2/3 */ > + MUX(CLK_MOUT_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 2), > + > + /* MIF0/1/2/3 */ > + MUX(CLK_MOUT_MIF_BUS, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, > + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), > + > + /* MISC */ > + MUX(CLK_MOUT_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), > + MUX(CLK_MOUT_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, > + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), > + > + /* PERI0 */ > + MUX(CLK_MOUT_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), > + MUX(CLK_MOUT_PERIC0_BUS, "mout_cmu_peric0_bus", mout_cmu_peric0_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), > + /* PERI1 */ > + MUX(CLK_MOUT_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), > + MUX(CLK_MOUT_PERIC1_BUS, "mout_cmu_peric1_bus", mout_cmu_peric1_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), > + > + /* TPU */ > + MUX(CLK_MOUT_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 2), > + > + MUX(CLK_MOUT_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", mout_cmu_tpu_tpuctl_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 2), > + > + MUX(CLK_MOUT_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 2), > + > + MUX(CLK_MOUT_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, > + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), > + > + /* BO */ > + MUX(CLK_MOUT_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, > + CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 2), > +}; > + > +static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { > + /* CMU_TOP_PURECLKCOMP */ > + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), > + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), > + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll", > + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 2), > + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", > + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), > + > + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), > + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), > + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "mout_shared1_pll", > + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), > + > + DIV(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll", > + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), > + > + DIV(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", "mout_shared3_pll", > + CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), > + > + /* BUS0 */ > + DIV(CLK_DOUT_BUS0_BUS, "dout_cmu_bus0_bus_div", "gout_cmu_bus0_bus", > + CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), > + DIV(CLK_DOUT_CMU_BOOST, "dout_cmu_boost", "gout_cmu_cmu_boost", > + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), > + > + /* BUS1 */ > + DIV(CLK_DOUT_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", > + CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), > + > + /* BUS2 */ > + DIV(CLK_DOUT_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", > + CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), > + > + /* CORE */ > + DIV(CLK_DOUT_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", > + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), > + > + /* EH */ > + DIV(CLK_DOUT_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", > + CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), > + > + /* CPUCL{0,1,2,} */ > + DIV(CLK_DOUT_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", "gout_cmu_cpucl2_switch", > + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), > + > + DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch", > + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), > + > + DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch", > + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), > + > + DIV(CLK_DOUT_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg", > + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), > + > + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", > + CLK_CON_DIV_CLKCMU_HPM, 0, 2), > + > + /* G3D */ > + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch", > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), > + > + DIV(CLK_DOUT_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", > + CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), > + > + DIV(CLK_DOUT_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", > + CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), > + > + /* DPU */ > + DIV(CLK_DOUT_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", > + CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), > + > + /* DISP */ > + DIV(CLK_DOUT_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", > + CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), > + > + /* G2D */ > + DIV(CLK_DOUT_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", > + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), > + > + DIV(CLK_DOUT_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", > + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), > + > + /* HSI0 */ > + DIV(CLK_DOUT_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd", > + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), > + > + DIV(CLK_DOUT_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", > + CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), > + > + DIV(CLK_DOUT_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc", > + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), > + > + /* TODO register exists but all lower bits are reserved */ > + DIV(CLK_DOUT_HSI0_USBDPDGB, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg", > + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0, 0), > + > + /* HSI1 */ > + DIV(CLK_DOUT_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", > + CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), > + > + DIV(CLK_DOUT_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", > + CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), > + /* HSI2 */ > + DIV(CLK_DOUT_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", > + CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), > + > + DIV(CLK_DOUT_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", > + CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), > + > + DIV(CLK_DOUT_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", "gout_cmu_hsi2_ufs_embd", > + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), > + > + DIV(CLK_DOUT_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", "gout_cmu_hsi2_mmc_card", > + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), > + > + /* CSIS */ > + DIV(CLK_DOUT_CSIS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", > + CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), > + > + /* PDP */ > + DIV(CLK_DOUT_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", > + CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), > + > + /* IPP */ > + DIV(CLK_DOUT_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", > + CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), > + > + /* G3AA */ > + DIV(CLK_DOUT_G3AA, "dout_cmu_g3aa", "gout_cmu_g3aa", > + CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), > + > + /* ITP */ > + DIV(CLK_DOUT_ITP, "dout_cmu_itp_bus", "gout_cmu_itp_bus", > + CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), > + > + /* DNS */ > + DIV(CLK_DOUT_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", > + CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), > + > + /* TNR */ > + DIV(CLK_DOUT_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", > + CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), > + > + /* MCSC*/ > + DIV(CLK_DOUT_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", > + CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), > + > + DIV(CLK_DOUT_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", > + CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), > + > + /* GDC */ > + DIV(CLK_DOUT_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", > + CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), > + > + DIV(CLK_DOUT_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", > + CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), > + > + DIV(CLK_DOUT_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", > + CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), > + > + /* MFC */ > + DIV(CLK_DOUT_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", > + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), > + > + /* MIF0/1/2/3 */ > + DIV(CLK_DOUT_MIF_BUS, "dout_cmu_mif_busp", "gout_cmu_mif_busp", > + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), > + > + /* MISC */ > + DIV(CLK_DOUT_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", > + CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), > + DIV(CLK_DOUT_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", > + CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), > + > + /* PERI0 */ > + DIV(CLK_DOUT_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus", > + CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), > + DIV(CLK_DOUT_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", > + CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), > + > + /* PERI1 */ > + DIV(CLK_DOUT_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus", > + CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), > + DIV(CLK_DOUT_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", > + CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), > + > + /* TPU */ > + DIV(CLK_DOUT_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", > + CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), > + > + DIV(CLK_DOUT_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", "gout_cmu_tpu_tpuctl", > + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), > + > + DIV(CLK_DOUT_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", > + CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), > + > + DIV(CLK_DOUT_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", > + CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), > + > + /* BO */ > + DIV(CLK_DOUT_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", > + CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), > + > +}; > + > +static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { > + /* CORE */ > + > + /* MISC */ > + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", > + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", > + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), > + > + /* BUS0 */ > + GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), > + > + /* BUS1 */ > + GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), > + > + /* BUS2 */ > + GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", > + CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), > + > + /* CORE */ > + GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", > + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), > + > + /* EH */ > + GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", > + CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), > + > + /* CPUCL{0,1,2,} */ > + GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", "mout_cmu_cpucl2_switch", > + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 21, 0, 0), > + > + GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch", > + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0), > + > + GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch", > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0), > + > + GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg", > + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0), > + > + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", > + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), > + > + /* G3D */ > + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch", > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), > + > + GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", > + CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), > + > + GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", > + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), > + /* DPU */ > + GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", > + CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), > + /* DISP */ > + GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", > + CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), > + > + /* G2D */ > + GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", > + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), > + > + GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", > + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), > + /* HSI0 */ > + GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", "mout_cmu_hsi0_usb31drd", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 21, 0, 0), > + > + GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), > + > + GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0), > + > + GATE(CLK_GOUT_HSI0_USBDPDGB, "gout_cmu_hsi0_usbdpdbg", "mout_cmu_hsi0_usbdpdbg", > + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 21, 0, 0), > + /* HSI1 */ > + GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), > + > + GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", > + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), > + /* HSI2 */ > + GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), > + GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), > + > + GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", "mout_cmu_hsi2_ufs_embd", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 21, 0, 0), > + GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", "mout_cmu_hsi2_mmc_card", > + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 21, 0, 0), > + /* CSIS */ > + GATE(CLK_GOUT_CSIS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", > + CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), > + /* PDP */ > + GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", > + CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), > + > + /* IPP */ > + GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", > + CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), > + /* G3AA */ > + GATE(CLK_GOUT_G3AA, "gout_cmu_g3aa", "mout_cmu_g3aa", > + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), > + > + /* ITP */ > + GATE(CLK_GOUT_ITP, "gout_cmu_itp_bus", "mout_cmu_itp_bus", > + CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), > + > + /* DNS */ > + GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", > + CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), > + > + /* TNR */ > + GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", > + CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), > + > + /* MCSC*/ > + GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", > + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), > + > + GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", > + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), > + > + /* GDC */ > + GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", > + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), > + > + GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), > + > + GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", > + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), > + > + /* MFC */ > + GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", > + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), > + > + /* DDRPHY0/1/2/3 */ > + GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch", > + CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), > + > + /* MIF0/1/2/3 */ > + GATE(CLK_GOUT_MIF_BUS, "gout_cmu_mif_busp", "mout_cmu_mif_busp", > + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), > + > + GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_boost", > + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), > + > + /* MISC */ > + GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", > + CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), > + GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", > + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), > + > + /* PERI0 */ > + GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus", > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", > + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), > + > + /* PERI1 */ > + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), > + > + /* TPU */ > + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), > + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0), > + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", > + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), > + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", > + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), > + > + /* BO */ > + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", > + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), > + > +}; > + > +static const struct samsung_cmu_info top_cmu_info __initconst = { > + .pll_clks = cmu_top_pll_clks, > + .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), > + .mux_clks = cmu_top_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), > + .div_clks = cmu_top_div_clks, > + .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), > + .gate_clks = cmu_top_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), > + .nr_clk_ids = TOP_NR_CLK, > + .clk_regs = cmu_top_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), > +}; > + > +static void __init gs101_cmu_top_init(struct device_node *np) > +{ > + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); > +} > + > +/* Register CMU_TOP early, as it's a dependency for other early domains */ > +CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > + gs101_cmu_top_init); > -- > 2.42.0.582.g8ccd20d70d-goog >
On 10/05/2023, Peter Griffin wrote: > This patch adds all the registers for the APM clock controller unit. > > We register all the muxes and dividers, but only a few of the > gates currently for PMU and GPIO. > > One clock is marked CLK_IS_CRITICAL because the system > hangs is this clock is disabled. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > drivers/clk/samsung/clk-gs101.c | 300 ++++++++++++++++++++++++++++++++ > 1 file changed, 300 insertions(+) > > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > index 4c58fcc899be..b98b42f54949 100644 > --- a/drivers/clk/samsung/clk-gs101.c > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -19,6 +19,7 @@ > > /* NOTE: Must be equal to the last clock ID increased by one */ > #define TOP_NR_CLK (CLK_GOUT_CMU_BOOST + 1) > +#define APM_NR_CLK (CLK_APM_PLL_DIV16_APM + 1) > > /* ---- CMU_TOP ------------------------------------------------------------- */ > > @@ -1556,3 +1557,302 @@ static void __init gs101_cmu_top_init(struct device_node *np) > /* Register CMU_TOP early, as it's a dependency for other early domains */ > CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", > gs101_cmu_top_init); > + > +/* ---- CMU_APM ------------------------------------------------------------- */ > +/* Register Offset definitions for CMU_APM (0x17400000) */ > +#define APM_CMU_APM_CONTROLLER_OPTION 0x0800 > +#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 > +#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 > +#define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 > +#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 > +#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c > +#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 > +#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 > +#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c > +#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 > +#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc > +#define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 > +#define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 > +#define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 > +#define PCH_CON_LHS_AXI_D_APM_PCH 0x300c > +#define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 > +#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 > +#define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 > +#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c > +#define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 > +#define QCH_CON_APBIF_RTC_QCH 0x3024 > +#define QCH_CON_APBIF_TRTC_QCH 0x3028 > +#define QCH_CON_APM_CMU_APM_QCH 0x302c > +#define QCH_CON_APM_USI0_UART_QCH 0x3030 > +#define QCH_CON_APM_USI0_USI_QCH 0x3034 > +#define QCH_CON_APM_USI1_UART_QCH 0x3038 > +#define QCH_CON_D_TZPC_APM_QCH 0x303c > +#define QCH_CON_GPC_APM_QCH 0x3040 > +#define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 > +#define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 > +#define QCH_CON_INTMEM_QCH 0x304c > +#define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 > +#define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 > +#define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 > +#define QCH_CON_LHS_AXI_D_APM_QCH 0x305c > +#define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 > +#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 > +#define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 > +#define QCH_CON_MAILBOX_APM_AP_QCH 0x306c > +#define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 > +#define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 > +#define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c > +#define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 > +#define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 > +#define QCH_CON_PMU_INTR_GEN_QCH 0x3088 > +#define QCH_CON_ROM_CRC32_HOST_QCH 0x308c > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 > +#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 > +#define QCH_CON_SPEEDY_APM_QCH 0x3098 > +#define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c > +#define QCH_CON_SSMT_D_APM_QCH 0x30a0 > +#define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 > +#define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 > +#define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac > +#define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 > +#define QCH_CON_SYSREG_APM_QCH 0x30b8 > +#define QCH_CON_UASC_APM_QCH 0x30bc > +#define QCH_CON_UASC_DBGCORE_QCH 0x30c0 > +#define QCH_CON_UASC_G_SWD_QCH 0x30c4 > +#define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 > +#define QCH_CON_UASC_P_APM_QCH 0x30cc > +#define QCH_CON_WDT_APM_QCH 0x30d0 > +#define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 > + > +static const unsigned long apm_clk_regs[] __initconst = { > + APM_CMU_APM_CONTROLLER_OPTION, > + CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, > + CLK_CON_DIV_DIV_CLK_APM_BOOST, > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, > + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, > + CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, > + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, > +}; > + > +PNAME(mout_apm_func_p) = { "oscclk_apm", "mout_apm_funcsrc", "pad_clk_apm", "oscclk_apm" }; > +PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", "pll_alv_div16_apm" }; > + > +static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { > + FRATE(CLK_APM_PLL_DIV2_APM, "clk_apm_pll_div2_apm", NULL, 0, 393216000), > + FRATE(CLK_APM_PLL_DIV4_APM, "clk_apm_pll_div4_apm", NULL, 0, 196608000), > + FRATE(CLK_APM_PLL_DIV16_APM, "clk_apm_pll_div16_apm", NULL, 0, 49152000), > +}; > + > +static const struct samsung_mux_clock apm_mux_clks[] __initconst = { > + MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), > + MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, > + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), > +}; > + > +static const struct samsung_div_clock apm_div_clks[] __initconst = { > + DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), > + DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), > + DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), > + DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", > + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), > +}; > + > +static const struct samsung_gate_clock apm_gate_clks[] __initconst = { > + GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", > + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_gpio_far_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, > + 21, 0, 0), > + > + GATE(CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + "gout_apm_pmu_alive_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, > + 21, CLK_IS_CRITICAL, 0), > + > + GATE(CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + "gout_apm_sysreg_apm_ipclkport_pclk", "gout_apm_func", > + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, > + 21, 0, 0), > +}; > + > +static const struct samsung_cmu_info apm_cmu_info __initconst = { > + .mux_clks = apm_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), > + .div_clks = apm_div_clks, > + .nr_div_clks = ARRAY_SIZE(apm_div_clks), > + .gate_clks = apm_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), > + .fixed_clks = apm_fixed_clks, > + .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), > + .nr_clk_ids = APM_NR_CLK, > + .clk_regs = apm_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), > +}; > + > +/* ---- platform_driver ----------------------------------------------------- */ > + > +static int __init gs101_cmu_probe(struct platform_device *pdev) > +{ > + const struct samsung_cmu_info *info; > + struct device *dev = &pdev->dev; > + > + info = of_device_get_match_data(dev); > + exynos_arm64_register_cmu(dev, dev->of_node, info); > + > + return 0; > +} > + > +static const struct of_device_id gs101_cmu_of_match[] = { > + { > + .compatible = "google,gs101-cmu-apm", > + .data = &apm_cmu_info, > + }, Missing terminating empty entry {}. Regards, Will > +}; > + > +static struct platform_driver gs101_cmu_driver __refdata = { > + .driver = { > + .name = "gs101-cmu", > + .of_match_table = gs101_cmu_of_match, > + .suppress_bind_attrs = true, > + }, > + .probe = gs101_cmu_probe, > +}; > + > +static int __init gs101_cmu_init(void) > +{ > + return platform_driver_register(&gs101_cmu_driver); > +} > +core_initcall(gs101_cmu_init); > -- > 2.42.0.582.g8ccd20d70d-goog >
On 05/10/2023 19:59, William McVicker wrote: > On 10/05/2023, Peter Griffin wrote: >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile >> phones. It features: >> * 4xA55 little cluster >> * 2xA76 Mid cluster >> * 2xX1 Big cluster >> >> This commit adds the basic device tree for gs101 (SoC) and oriole >> (pixel 6). Further platform support will be added over time. >> >> It has been tested with a minimal busybox initramfs and boots to >> a shell. >> >> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> >> --- >> arch/arm64/Kconfig.platforms | 6 + >> arch/arm64/boot/dts/Makefile | 1 + >> arch/arm64/boot/dts/google/Makefile | 6 + >> arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + >> arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++++++++++ >> arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + >> arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++++++ >> 7 files changed, 1733 insertions(+) >> create mode 100644 arch/arm64/boot/dts/google/Makefile >> create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts >> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi >> create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h >> create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi >> >> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms >> index 6069120199bb..a5ed1b719488 100644 >> --- a/arch/arm64/Kconfig.platforms >> +++ b/arch/arm64/Kconfig.platforms >> @@ -107,6 +107,12 @@ config ARCH_EXYNOS >> help >> This enables support for ARMv8 based Samsung Exynos SoC family. >> >> +config ARCH_GOOGLE_TENSOR >> + bool "Google Tensor SoC fmaily" >> + depends on ARCH_EXYNOS >> + help >> + Support for ARMv8 based Google Tensor platforms. > > I'd like to bring up this thread and discuss the option of not introducing > another ARCH_* config: > > https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ > > I especially don't like the "depends on ARCH_EXYNOS" because that forces one to > include all the other Exynos drivers that ARCH_EXYNOS selects that Google Since we are creating unified kernel images, having other drivers is not a problem. > Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all SOC_GOOGLE will work exactly the same and depend on ARCH_EXYNOS or appear everywhere as ARCH_EXYNOS. We already had this talk with Tesla. > drivers that actually depend on the SoC hardware, we can just add "depends on > SOC_GOOGLE"? > > The idea is that drivers should be tied to hardware -- not a specific vendor. And hardware is Exynos. Tesla FSD and Google Tensor is Exynos, even if you do no like calling it. > By making drivers depend on ARCH_*, you are introducing an arbitrary vendor > dependency and not a hardware dependency. There is no arbitrary dependency. We call it all Exynos hardware, because this is Exynos. I remember what you were pushing for removal of ARCH_EXYNOS and there waas clear feedback, not only from me: this is against communities goals. > > Thanks, > Will Please trim the replies from unrelated context. Best regards, Krzysztof
On 10/05/2023, Krzysztof Kozlowski wrote: > On 05/10/2023 19:59, William McVicker wrote: > > On 10/05/2023, Peter Griffin wrote: > >> Google gs101 SoC is ARMv8 mobile SoC found in the Pixel 6, > >> (oriole) Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > >> phones. It features: > >> * 4xA55 little cluster > >> * 2xA76 Mid cluster > >> * 2xX1 Big cluster > >> > >> This commit adds the basic device tree for gs101 (SoC) and oriole > >> (pixel 6). Further platform support will be added over time. > >> > >> It has been tested with a minimal busybox initramfs and boots to > >> a shell. > >> > > William, > > Please do not Cc non-existing mailboxes. You added Cc kernel-team and we > all got awesome bounces now: > > "We're writing to let you know that the group you tried to contact > (kernel-team) may not exist, or you may not have permission to post > messages to the group. A few more details on why you weren't able to post:" > > Best regards, > Krzysztof > Sorry, I mistyped the email. Should have been kernel-team@android.com. Regards, Will
On 10/05/2023, Krzysztof Kozlowski wrote: > On 05/10/2023 21:23, Greg KH wrote: > > On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote: > >>>> I'd like to bring up this thread and discuss the option of not introducing > >>>> another ARCH_* config: > >>>> > >>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ > >>> > >>> I agree, PLEASE don't add platform config options as that makes it > >>> impossible to make a unified kernel image that works for more than one > >>> platform at the same time. > >> > >> There is no single problem in making unified image as we were doing > >> since beginning of ARM64. The ARCH_* is not a obstacle for this. > > > > Then why are the ARCH_* options needed at all? What does this help out > > with? > > It helps all the people and distros who do not want to build/package > drivers or modules for unrelated hardware or architectures. > > Let's take Samsung Exynos UART driver. It will never, 100% never, work > on x86, x86_64. There is no single need to package it for kernels build > for these products. It will not work on nVidia Tegra ARM64, Qualcomm > ARM64 SoC, so if you do not want to run on Exynos, then you do no select > ARCH_EXYNOS and have significantly smaller image. > > Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm > + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS > or SOC_GOOGLE serves only the purpose to allow distros and people > customize build for specific hardware. > > It does not limit anyone on anything. I'm glad you brought up Exynos UART because this is where one of the limitations is introduced. For example, if you want to modularize out all the vendor specific drivers from the core kernel to create a common arm64 kernel binary that works on all ARM64 devices, you will not be able to build in the early console UART drivers without enabling the respective ARCH_* configs. Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for debugging early boot issues. I understand that ARCH_* configs are used to selectively pick which device tree blobs are built, but forcing developers to pick all or nothing is where I have a problem. Regards, Will > > > > > > >>>> I especially don't like the "depends on ARCH_EXYNOS" because that forces one to > >>>> include all the other Exynos drivers that ARCH_EXYNOS selects that Google > >>>> Tensor SoCs don't need. Can we consider using SOC_GOOGLE instead and for all > >>>> drivers that actually depend on the SoC hardware, we can just add "depends on > >>>> SOC_GOOGLE"? > >>> > >>> Why do any of this at all? It should not be needed. > >>> > >>>> The idea is that drivers should be tied to hardware -- not a specific vendor. > >>> > >>> And drivers should be auto-loaded. > >>> > >>> All of these drivers are not vendor-specific at all, they are based on > >>> the same IP blocks as others, so that is how they should be unified. > >> > >> They are vendor specific. All of them are specifically for Exynos > >> hardwre, because this is Exynos. We call it Google GS/Tensor SoC just > >> for fancy convenience, but this just Exynos. > > > > Ok, then why is this ARCH_ option needed if these IP blocks really are > > from something else and are part of other drivers? > > For the same reason above, because if I want to build kernel for > Qualcomm, I want to drop easily anything not related. If I want to build > kernel without I2C, I disable I2C bus which effectively disables all > drivers which work on I2C. If I want to build kernel without Exynos, I > disable ARCH_EXYNOS which effectively disables entire Exynos hardware. > > Think of SoC as a bus or interface. > > Best regards, > Krzysztof >
On 06/10/2023 01:19, William McVicker wrote: > On 10/05/2023, Krzysztof Kozlowski wrote: >> On 05/10/2023 21:23, Greg KH wrote: >>> On Thu, Oct 05, 2023 at 09:18:48PM +0200, Krzysztof Kozlowski wrote: >>>>>> I'd like to bring up this thread and discuss the option of not introducing >>>>>> another ARCH_* config: >>>>>> >>>>>> https://lore.kernel.org/all/20200306103652.GA3634389@kroah.com/ >>>>> >>>>> I agree, PLEASE don't add platform config options as that makes it >>>>> impossible to make a unified kernel image that works for more than one >>>>> platform at the same time. >>>> >>>> There is no single problem in making unified image as we were doing >>>> since beginning of ARM64. The ARCH_* is not a obstacle for this. >>> >>> Then why are the ARCH_* options needed at all? What does this help out >>> with? >> >> It helps all the people and distros who do not want to build/package >> drivers or modules for unrelated hardware or architectures. >> >> Let's take Samsung Exynos UART driver. It will never, 100% never, work >> on x86, x86_64. There is no single need to package it for kernels build >> for these products. It will not work on nVidia Tegra ARM64, Qualcomm >> ARM64 SoC, so if you do not want to run on Exynos, then you do no select >> ARCH_EXYNOS and have significantly smaller image. >> >> Now, there is no problem to have one kernel for nVidia Tegra + Qualcomm >> + Samsung Exynos with everything you need. The ARCH_EXYNOS or SOC_EXYNOS >> or SOC_GOOGLE serves only the purpose to allow distros and people >> customize build for specific hardware. >> >> It does not limit anyone on anything. > > I'm glad you brought up Exynos UART because this is where one of the > limitations is introduced. For example, if you want to modularize out all the > vendor specific drivers from the core kernel to create a common arm64 kernel > binary that works on all ARM64 devices, you will not be able to build in the > early console UART drivers without enabling the respective ARCH_* configs. When you build single kernel there is never need to NOT ENABLE respective ARCH configs. Please describe me upstream case for such need to NOT ENABLE. > Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very valuable for > debugging early boot issues. Really? How related? The drivers are independent. You describe some out-of-tree development process which we never needed for upstream work. And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > > I understand that ARCH_* configs are used to selectively pick which device tree > blobs are built, but forcing developers to pick all or nothing is where I have > a problem. No one forces you to pick up everything or nothing. You select ARCH_EXYNOS and still can drop all optional drivers. It's true you cannot drop mandatory drivers, but you are upstreaming Exynos platform, right? We do not talk about your out-of-tree Google work because it does not matter. Best regards, Krzysztof
On 05/10/2023 17:56, Peter Griffin wrote: > Add support for the pin-controller found on the gs101 > SoC used in Pixel 6 phones. > > The alive blocks on this SoC also have a filter selection > register. Add support for this so the digital or delay filter > can be selected. If the filter selection is not available > then the default filter (digital) is applied. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++- > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++ > 5 files changed, 302 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > index cb965cf93705..ae681725db26 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { > .ctrl = fsd_pin_ctrl, > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), > }; > + > +/* > + * bank type for non-alive type > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > + * (CONPDN bit field: 2, PUDPDN bit field: 4) > + */ > +static struct samsung_pin_bank_type bank_type_6 = { Bank types are defined at the top. "type_6" is way too vague. Look how the others are named. > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > +}; > + > +/* > + * bank type for alive type > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > + */ > +static const struct samsung_pin_bank_type bank_type_7 = { Same problem. > + .fld_width = { 4, 1, 4, 4, }, > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > +}; > + > +/* pin banks of gs101 pin-controller (ALIVE) */ > +static const struct samsung_pin_bank_data gs101_pin_alive[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE), > +}; > + > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE), > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE), > +}; > + > +/* pin banks of gs101 pin-controller (GSACORE) */ > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (GSACTRL) */ > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (PERIC0) */ > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (PERIC1) */ > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (HSI1) */ > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT), > +}; > + > +/* pin banks of gs101 pin-controller (HSI2) */ > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT), > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT), > +}; > + > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { > + { > + /* pin banks of gs101 pin-controller (ALIVE) */ > + .pin_banks = gs101_pin_alive, > + .nr_banks = ARRAY_SIZE(gs101_pin_alive), > + .eint_gpio_init = exynos_eint_gpio_init, > + .eint_wkup_init = exynos_eint_wkup_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ > + .pin_banks = gs101_pin_far_alive, > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), > + .eint_gpio_init = exynos_eint_gpio_init, > + .eint_wkup_init = exynos_eint_wkup_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (GSACORE) */ > + .pin_banks = gs101_pin_gsacore, > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), > + .eint_gpio_init = exynos_eint_gpio_init, > + }, { > + /* pin banks of gs101 pin-controller (GSACTRL) */ > + .pin_banks = gs101_pin_gsactrl, > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), > + .eint_gpio_init = exynos_eint_gpio_init, > + }, { > + /* pin banks of gs101 pin-controller (PERIC0) */ > + .pin_banks = gs101_pin_peric0, > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (PERIC1) */ > + .pin_banks = gs101_pin_peric1, > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (HSI1) */ > + .pin_banks = gs101_pin_hsi1, > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, { > + /* pin banks of gs101 pin-controller (HSI2) */ > + .pin_banks = gs101_pin_hsi2, > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), > + .eint_gpio_init = exynos_eint_gpio_init, > + .suspend = exynos_pinctrl_suspend, > + .resume = exynos_pinctrl_resume, > + }, > +}; > + > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { > + .ctrl = gs101_pin_ctrl, > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), > +}; > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > index a8212fc126bf..0c6c3312abb7 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save { > u32 eint_mask; > }; Please split the patch into two: one of adding new filter code and second for new Google SoC. > > +static void exynos_eint_flt_config(int sel, int width, > + struct samsung_pinctrl_drv_data *d, > + struct samsung_pin_bank *bank) Arguments: first drv_data, then bank, then width, then sel... and what is sel actually? Also, why do you need width if it is always 0? Will it be different in next pinctrl controllers? So the filter is per entire bank? > +{ > + unsigned int flt_reg, flt_con = 0; > + unsigned int val, shift; > + int i; > + int loop_cnt; > + > + flt_con |= EXYNOS_FLTCON_EN; > + > + if (sel) > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL; > + > + flt_con |= EXYNOS_FLTCON_WIDTH(width); This is always 0, what's the point? > + > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > + > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > + /* > + * if nr_pins > 4, we should set FLTCON0 register fully. > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > + */ > + loop_cnt = 4; > + else > + loop_cnt = bank->nr_pins; Please document the layout of the registers in exynos_eint_flt_config() comment (not kerneldoc). Also document what do you want to achieve here - set entire bank to one filter for the suspend/resume? > + > + val = readl(d->virt_base + flt_reg); > + > + for (i = 0; i < loop_cnt; i++) { > + shift = i * EXYNOS_FLTCON_LEN; > + val &= ~(EXYNOS_FLTCON_MASK << shift); > + val |= (flt_con << shift); > + } > + > + writel(val, d->virt_base + flt_reg); > + Missing /* > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0. > + * (pin4 ~ ) > + */ > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > + writel(val, d->virt_base + flt_reg + 0x4); > +} > + > /* > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > * @d: driver data of samsung pinctrl driver. > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > goto err_domains; > } > > + /* Set Delay Analog Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > + 0, d, bank); > } > > return 0; > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > if (bank->eint_type != EINT_TYPE_WKUP) > continue; > > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > + 0, d, bank); > + > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > GFP_KERNEL); > if (!bank->irq_chip) { > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank( > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > struct exynos_irq_chip *irq_chip = NULL; > int i; > > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > if (bank->eint_type == EINT_TYPE_GPIO) > exynos_pinctrl_suspend_bank(drvdata, bank); > else if (bank->eint_type == EINT_TYPE_WKUP) { > + /* Setting Delay (Analog) Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > + 0, d, bank); > if (!irq_chip) { > irq_chip = bank->irq_chip; > irq_chip->set_eint_wakeup_mask(drvdata, > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank( > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > { > struct samsung_pin_bank *bank = drvdata->pin_banks; > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > int i; > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > - if (bank->eint_type == EINT_TYPE_GPIO) > + if (bank->eint_type == EINT_TYPE_GPIO) { > exynos_pinctrl_resume_bank(drvdata, bank); > + } else if (bank->eint_type == EINT_TYPE_WKUP || > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > + /* Set Digital Filter */ > + if (bank->fltcon_type != FLT_DEFAULT) > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > + 0, d, bank); > + } > } > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > index 7bd6d82c9f36..aafd8f9f52f8 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > @@ -16,6 +16,8 @@ > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H > #define __PINCTRL_SAMSUNG_EXYNOS_H > > +#include <linux/bitfield.h> > + I don't think you use in this header anything from bitfield. > /* Values for the pin CON register */ > #define EXYNOS_PIN_CON_FUNC_EINT 0xf > > @@ -50,6 +52,14 @@ > > #define EXYNOS_EINT_MAX_PER_BANK 8 > #define EXYNOS_EINT_NR_WKUP_EINT > +/* EINT filter configuration */ > +#define EXYNOS_FLTCON_EN BIT(7) EXYNOS9? Earlier variants did not have it, AFAIR. > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6) > +#define EXYNOS_FLTCON_SEL_DELAY 0 > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f) > +#define EXYNOS_FLTCON_MASK 0xFF Keep lowercase hex > +#define EXYNOS_FLTCON_LEN 8 > +#define EXYNOS_FLTCON_NR_PIN 4 > > #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ > { \ > @@ -140,6 +150,40 @@ > .name = id \ > } Best regards, Krzysztof
On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > On 06/10/2023 01:19, William McVicker wrote: >> On 10/05/2023, Krzysztof Kozlowski wrote: >>> On 05/10/2023 21:23, Greg KH wrote: >> >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > valuable for >> debugging early boot issues. > > Really? How related? The drivers are independent. You describe some > out-of-tree development process which we never needed for upstream work. > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. Right: in general, all drivers are independent of the platform besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, but I think it's worth mentioning the known exceptions, so Greg and Will can take that fight to the respective places rather than discussing it in the platform submission: - Some subsystems are considered 'special' and the maintainers prefer the drivers to be automatically selected based on the ARCH_* settings instead of having user-visible options. This is traditionally true for large chunks of drivers/irqchip, drivers/clocksource and drivers/pinctrl, though it has gotten better over time on all of them. - Some older 32-bit platforms are still not as modular as we'd like them to be, especially the StrongARM (ARMv4) platforms that require a custom kernel build, and some of ARMv4T and ARMv5 boards that are still missing DT support. These tend to require drivers they directly link to from board code, so disabling the drivers would cause a link failure until this gets cleaned up. - A couple of drivers are force-enabled based on the ARCH_* options because booting without these drivers would risk permanent damage to hardware, e.g. in overtemp or overcurrent scenarios. - ACPI based platforms require the PCI host bridge driver to be built-in rather than a loadable module because ACPI needs to probe PCI devices during early boot. - Some subsystems (notably drivers/gpu/, but others as well) have an excessive number of 'select' statements, so you end up surprise-enabling a number of additional drivers and subsystems by enabling certain less important platform specific drivers. Arnd
On 10/06/2023, Arnd Bergmann wrote: > On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > > On 06/10/2023 01:19, William McVicker wrote: > >> On 10/05/2023, Krzysztof Kozlowski wrote: > >>> On 05/10/2023 21:23, Greg KH wrote: > >> > >> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > > valuable for > >> debugging early boot issues. > > > > Really? How related? The drivers are independent. You describe some > > out-of-tree development process which we never needed for upstream work. > > And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > > Right: in general, all drivers are independent of the platform > besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, > but I think it's worth mentioning the known exceptions, so Greg and > Will can take that fight to the respective places rather than > discussing it in the platform submission: > > - Some subsystems are considered 'special' and the maintainers > prefer the drivers to be automatically selected based on the > ARCH_* settings instead of having user-visible options. This is > traditionally true for large chunks of drivers/irqchip, > drivers/clocksource and drivers/pinctrl, though it has gotten > better over time on all of them. > > - Some older 32-bit platforms are still not as modular as we'd > like them to be, especially the StrongARM (ARMv4) platforms that > require a custom kernel build, and some of ARMv4T and ARMv5 > boards that are still missing DT support. These tend to require > drivers they directly link to from board code, so disabling > the drivers would cause a link failure until this gets > cleaned up. > > - A couple of drivers are force-enabled based on the ARCH_* > options because booting without these drivers would risk > permanent damage to hardware, e.g. in overtemp or overcurrent > scenarios. > > - ACPI based platforms require the PCI host bridge driver to > be built-in rather than a loadable module because ACPI > needs to probe PCI devices during early boot. > > - Some subsystems (notably drivers/gpu/, but others as well) > have an excessive number of 'select' statements, so you > end up surprise-enabling a number of additional drivers > and subsystems by enabling certain less important platform > specific drivers. > > Arnd So if the argument is that the existing upstream Exynos platforms are required to have these drivers built-in to the kernel to boot: COMMON_CLK_SAMSUNG CLKSRC_EXYNOS_MCT EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS EXYNOS_PMU PINCTRL PINCTRL_EXYNOS PM_GENERIC_DOMAINS if PM SOC_SAMSUNG ...then that is understandable and we can work to fix that. My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in the platform Kconfig? For example, I don't really like this: diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027..4c8f173c4dec 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and so on? How are we going to pick the right driver when we have a generic ARCH_GOOGLE_TENSOR config? Ideally, we should have one Exynos clock driver that can detect what hardware is running (using the DT) to determine what it needs to do. If you really want to compile out the other vendor's clock drivers using some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD configs (not ideal though). With that approach, we could drop the platform ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. Let me know your thoughts. Thanks, Will
On Thu, Oct 5, 2023 at 6:04 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 05/10/2023 17:55, Peter Griffin wrote: > > Add the gs101 SoC interrupt header that provides human readable > > constants for all the IRQs in the SoC. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > +#define ITNO IRQ_TYPE_NONE > > +#define ITER IRQ_TYPE_EDGE_RISING > > +#define ITEF IRQ_TYPE_EDGE_FALLING > > +#define ITEB IRQ_TYPE_EDGE_BOTH > > +#define ITLH IRQ_TYPE_LEVEL_HIGH > > +#define ITLL IRQ_TYPE_LEVEL_LOW > > No, these are not bindings. > > > + > > +#define IRQ_ALIVE_EINT0 0 > > +#define IRQ_ALIVE_EINT1 1 > > We do not keep interrupt numbers as bindings. Please drop entire file. Agree, but it should be fine to have as a SoC-specific .dtsi under arch/.../google/gs101-irq.dtsi though! Yours, Linus Walleij
On 06/10/2023 18:33, William McVicker wrote: > On 10/06/2023, Arnd Bergmann wrote: >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: >>> On 06/10/2023 01:19, William McVicker wrote: >>>> On 10/05/2023, Krzysztof Kozlowski wrote: >>>>> On 05/10/2023 21:23, Greg KH wrote: >>>> >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very >>> valuable for >>>> debugging early boot issues. >>> >>> Really? How related? The drivers are independent. You describe some >>> out-of-tree development process which we never needed for upstream work. >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. >> >> Right: in general, all drivers are independent of the platform >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, >> but I think it's worth mentioning the known exceptions, so Greg and >> Will can take that fight to the respective places rather than >> discussing it in the platform submission: >> >> - Some subsystems are considered 'special' and the maintainers >> prefer the drivers to be automatically selected based on the >> ARCH_* settings instead of having user-visible options. This is >> traditionally true for large chunks of drivers/irqchip, >> drivers/clocksource and drivers/pinctrl, though it has gotten >> better over time on all of them. >> >> - Some older 32-bit platforms are still not as modular as we'd >> like them to be, especially the StrongARM (ARMv4) platforms that >> require a custom kernel build, and some of ARMv4T and ARMv5 >> boards that are still missing DT support. These tend to require >> drivers they directly link to from board code, so disabling >> the drivers would cause a link failure until this gets >> cleaned up. >> >> - A couple of drivers are force-enabled based on the ARCH_* >> options because booting without these drivers would risk >> permanent damage to hardware, e.g. in overtemp or overcurrent >> scenarios. >> >> - ACPI based platforms require the PCI host bridge driver to >> be built-in rather than a loadable module because ACPI >> needs to probe PCI devices during early boot. >> >> - Some subsystems (notably drivers/gpu/, but others as well) >> have an excessive number of 'select' statements, so you >> end up surprise-enabling a number of additional drivers >> and subsystems by enabling certain less important platform >> specific drivers. >> >> Arnd > > So if the argument is that the existing upstream Exynos platforms are required > to have these drivers built-in to the kernel to boot: > COMMON_CLK_SAMSUNG > CLKSRC_EXYNOS_MCT > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS > EXYNOS_PMU > PINCTRL > PINCTRL_EXYNOS > PM_GENERIC_DOMAINS if PM > SOC_SAMSUNG > > ...then that is understandable and we can work to fix that. > > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in > the platform Kconfig? For example, I don't really like this: > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > index 76a494e95027..4c8f173c4dec 100644 > --- a/drivers/clk/samsung/Kconfig > +++ b/drivers/clk/samsung/Kconfig > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR > > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and > so on? Nothing happens... or happens anything you wish. Did you read the motivation why this was created like this? > How are we going to pick the right driver when e have a generic > ARCH_GOOGLE_TENSOR config? You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick is done by you. Nothing to do more. > Ideally, we should have one Exynos clock driver that > can detect what hardware is running (using the DT) to determine what it needs It's already like this. We're done. > to do. If you really want to compile out the other vendor's clock drivers using > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD Whether you call it SOC or ARCH it is the same. We organized it as ARCH. > configs (not ideal though). With that approach, we could drop the platform > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. There is no need for this. ARCH does exactly the same. Best regards, Krzysztof
Hi Krzysztof, Firstly, thankyou for all your reviews. It's much appreciated. On Fri, 6 Oct 2023 at 07:33, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:56, Peter Griffin wrote: > > Add support for the pin-controller found on the gs101 > > SoC used in Pixel 6 phones. > > > > The alive blocks on this SoC also have a filter selection > > register. Add support for this so the digital or delay filter > > can be selected. If the filter selection is not available > > then the default filter (digital) is applied. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++ > > drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +++++++- > > drivers/pinctrl/samsung/pinctrl-exynos.h | 44 +++++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 24 +++ > > 5 files changed, 302 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > index cb965cf93705..ae681725db26 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { > > .ctrl = fsd_pin_ctrl, > > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), > > }; > > + > > +/* > > + * bank type for non-alive type > > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > > + * (CONPDN bit field: 2, PUDPDN bit field: 4) > > + */ > > +static struct samsung_pin_bank_type bank_type_6 = { > > Bank types are defined at the top. "type_6" is way too vague. Look how > the others are named. Will fix > > > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > > +}; > > + > > +/* > > + * bank type for alive type > > + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) > > + */ > > +static const struct samsung_pin_bank_type bank_type_7 = { > > Same problem. Will fix > > > + .fld_width = { 4, 1, 4, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > +}; > > + > > +/* pin banks of gs101 pin-controller (ALIVE) */ > > +static const struct samsung_pin_bank_data gs101_pin_alive[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE), > > +}; > > + > > +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ > > +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE), > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE), > > +}; > > + > > +/* pin banks of gs101 pin-controller (GSACORE) */ > > +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (GSACTRL) */ > > +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { > > + EXYNOS9_PIN_BANK_EINTW(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (PERIC0) */ > > +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (PERIC1) */ > > +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (HSI1) */ > > +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT), > > +}; > > + > > +/* pin banks of gs101 pin-controller (HSI2) */ > > +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT), > > + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT), > > +}; > > + > > +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { > > + { > > + /* pin banks of gs101 pin-controller (ALIVE) */ > > + .pin_banks = gs101_pin_alive, > > + .nr_banks = ARRAY_SIZE(gs101_pin_alive), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ > > + .pin_banks = gs101_pin_far_alive, > > + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (GSACORE) */ > > + .pin_banks = gs101_pin_gsacore, > > + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + }, { > > + /* pin banks of gs101 pin-controller (GSACTRL) */ > > + .pin_banks = gs101_pin_gsactrl, > > + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + }, { > > + /* pin banks of gs101 pin-controller (PERIC0) */ > > + .pin_banks = gs101_pin_peric0, > > + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (PERIC1) */ > > + .pin_banks = gs101_pin_peric1, > > + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (HSI1) */ > > + .pin_banks = gs101_pin_hsi1, > > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, { > > + /* pin banks of gs101 pin-controller (HSI2) */ > > + .pin_banks = gs101_pin_hsi2, > > + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > + }, > > +}; > > + > > +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { > > + .ctrl = gs101_pin_ctrl, > > + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), > > +}; > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c > > index a8212fc126bf..0c6c3312abb7 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c > > @@ -269,6 +269,50 @@ struct exynos_eint_gpio_save { > > u32 eint_mask; > > }; > > Please split the patch into two: one of adding new filter code and > second for new Google SoC. Will do > > > > > +static void exynos_eint_flt_config(int sel, int width, > > + struct samsung_pinctrl_drv_data *d, > > + struct samsung_pin_bank *bank) > > Arguments: first drv_data, then bank, then width, then sel... and what > is sel actually? Will fix. Sel parameter is just setting the FLT_SEL bitfield 0 = Delay filter 1 = Digital filter > > Also, why do you need width if it is always 0? Will it be different in > next pinctrl controllers? The downstream driver never set the width bitfield so I we could remove this width logic and add it back if it's ever required. > So the filter is per entire bank? The filter is selectable per pin. So each pin has a FLT_EN, FLT_SEL and FLT_WIDTH bitfield. > > > +{ > > + unsigned int flt_reg, flt_con = 0; > > + unsigned int val, shift; > > + int i; > > + int loop_cnt; > > + > > + flt_con |= EXYNOS_FLTCON_EN; > > + > > + if (sel) > > + flt_con |= EXYNOS_FLTCON_SEL_DIGITAL; > > + > > + flt_con |= EXYNOS_FLTCON_WIDTH(width); > > This is always 0, what's the point? Yeah we could remove this, and add it back if it's ever required. Let me know if that's what you prefer? > > > + > > + flt_reg = EXYNOS_GPIO_EFLTCON_OFFSET + bank->fltcon_offset; > > + > > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > > + /* > > + * if nr_pins > 4, we should set FLTCON0 register fully. > > + * (pin0 ~ 3). So loop 4 times in case of FLTCON0. > > + */ > > + loop_cnt = 4; > > + else > > + loop_cnt = bank->nr_pins; > > Please document the layout of the registers in exynos_eint_flt_config() > comment (not kerneldoc). Also document what do you want to achieve here > - set entire bank to one filter for the suspend/resume? Yes exactly it is looping through setting all the pins in the bank to one filter on suspend and resume. I will add a comment as you suggest. > > > + > > + val = readl(d->virt_base + flt_reg); > > + > > + for (i = 0; i < loop_cnt; i++) { > > + shift = i * EXYNOS_FLTCON_LEN; > > + val &= ~(EXYNOS_FLTCON_MASK << shift); > > + val |= (flt_con << shift); > > + } > > + > > + writel(val, d->virt_base + flt_reg); > > + > > Missing /* Will fix > > > + /* if nr_pins > 4, we should also set FLTCON1 register like FLTCON0. > > + * (pin4 ~ ) > > + */ > > + if (bank->nr_pins > EXYNOS_FLTCON_NR_PIN) > > + writel(val, d->virt_base + flt_reg + 0x4); > > +} > > + > > /* > > * exynos_eint_gpio_init() - setup handling of external gpio interrupts. > > * @d: driver data of samsung pinctrl driver. > > @@ -321,6 +365,10 @@ __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) > > goto err_domains; > > } > > > > + /* Set Delay Analog Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > > + 0, d, bank); > > } > > > > return 0; > > @@ -555,6 +603,11 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) > > if (bank->eint_type != EINT_TYPE_WKUP) > > continue; > > > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > > + 0, d, bank); > > + > > bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), > > GFP_KERNEL); > > if (!bank->irq_chip) { > > @@ -658,6 +711,7 @@ static void exynos_pinctrl_suspend_bank( > > void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > struct exynos_irq_chip *irq_chip = NULL; > > int i; > > > > @@ -665,6 +719,10 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) > > if (bank->eint_type == EINT_TYPE_GPIO) > > exynos_pinctrl_suspend_bank(drvdata, bank); > > else if (bank->eint_type == EINT_TYPE_WKUP) { > > + /* Setting Delay (Analog) Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DELAY, > > + 0, d, bank); > > if (!irq_chip) { > > irq_chip = bank->irq_chip; > > irq_chip->set_eint_wakeup_mask(drvdata, > > @@ -707,11 +765,19 @@ static void exynos_pinctrl_resume_bank( > > void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) > > { > > struct samsung_pin_bank *bank = drvdata->pin_banks; > > + struct samsung_pinctrl_drv_data *d = bank->drvdata; > > int i; > > > > for (i = 0; i < drvdata->nr_banks; ++i, ++bank) > > - if (bank->eint_type == EINT_TYPE_GPIO) > > + if (bank->eint_type == EINT_TYPE_GPIO) { > > exynos_pinctrl_resume_bank(drvdata, bank); > > + } else if (bank->eint_type == EINT_TYPE_WKUP || > > + bank->eint_type == EINT_TYPE_WKUP_MUX) { > > + /* Set Digital Filter */ > > + if (bank->fltcon_type != FLT_DEFAULT) > > + exynos_eint_flt_config(EXYNOS_FLTCON_SEL_DIGITAL, > > + 0, d, bank); > > + } > > } > > > > static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h > > index 7bd6d82c9f36..aafd8f9f52f8 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos.h > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h > > @@ -16,6 +16,8 @@ > > #ifndef __PINCTRL_SAMSUNG_EXYNOS_H > > #define __PINCTRL_SAMSUNG_EXYNOS_H > > > > +#include <linux/bitfield.h> > > + > > I don't think you use in this header anything from bitfield. > > > /* Values for the pin CON register */ > > #define EXYNOS_PIN_CON_FUNC_EINT 0xf > > > > @@ -50,6 +52,14 @@ > > > > #define EXYNOS_EINT_MAX_PER_BANK 8 > > #define EXYNOS_EINT_NR_WKUP_EINT > > +/* EINT filter configuration */ > > +#define EXYNOS_FLTCON_EN BIT(7) > > EXYNOS9? Earlier variants did not have it, AFAIR. Will fix > > > +#define EXYNOS_FLTCON_SEL_DIGITAL BIT(6) > > +#define EXYNOS_FLTCON_SEL_DELAY 0 > > +#define EXYNOS_FLTCON_WIDTH(x) ((x) & 0x3f) > > +#define EXYNOS_FLTCON_MASK 0xFF > > Keep lowercase hex Will fix Kind regards, Peter.
On 05/10/2023 17:55, Peter Griffin wrote: > Hi folks, > > This series adds initial SoC support for the GS101 SoC and also initial board > support for Pixel 6 phone (Oriole). > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > Currently DT is just added for the gs101 SoC and Oriole. > > The support added in this series consists of: > * cpus > * pinctrl > * some CCF clock implementation > * watchdog > * uart > * gpio Hi Peter, Heads up, in case you are not aware Arm SoC timeframes: we are at rc5, so it means that anything targeting v6.7 should be applied this working week, before rc6. At least as ARM SoC is concerned. Best regards, Krzysztof
Hi Krzysztof, On Thu, 5 Oct 2023 at 17:32, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:55, Peter Griffin wrote: > > Hi folks, > > > > This series adds initial SoC support for the GS101 SoC and also initial board > > support for Pixel 6 phone (Oriole). > > > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > > Currently DT is just added for the gs101 SoC and Oriole. > > Thanks for submitting the patches. Nice work! Thanks, and thankyou for reviewing the series so promptly. > > This is basically a custom-made variant of Exynos made by Samsung for > Google. Something similar what is with Tesla FSD (and Axis Artpec-8 > which was not upstreamed, AFAIR). Many, many drivers and bindings will > be re-used. I want to be sure that GS101 fits into existing Samsung > Exynos support, re-uses it as much as possible and extend when necessary > without breaking anything. Therefore, when the patches are ready, I > would like to be the one applying entire set and future submissions > through Samsung SoC tree, just like I am doing it with Tesla FSD, so I > keep entire Samsung-ecosystem in shape. > > This also means that you are lucky to be selected to: > https://elixir.bootlin.com/linux/v6.6-rc4/source/Documentation/process/maintainer-soc-clean-dts.rst > joining there Tesla FSD and entire Samsung Exynos family :) > > I hope that's ok. That's all fine, it makes sense and it was what I was expecting. Maybe we can try and get you some Pixel 6 hardware as well. The only other Exynos hardware I have for testing unfortunately is the e850 board Sam has been working on. Coincidentally https://www.crowdsupply.com/0xda/usb-cereal just started shipping. Which is quite nice (albeit coincidental) timing, as anyone who has a Pixel 6 device can order one so they can run upstream kernels on their phone and have the debug UART available (which currently is the only way to really interact with the system until we bring up more IO). regards, Peter
Hi Krzysztof, On Mon, 9 Oct 2023 at 12:10, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 05/10/2023 17:55, Peter Griffin wrote: > > Hi folks, > > > > This series adds initial SoC support for the GS101 SoC and also initial board > > support for Pixel 6 phone (Oriole). > > > > The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). > > Currently DT is just added for the gs101 SoC and Oriole. > > > > The support added in this series consists of: > > * cpus > > * pinctrl > > * some CCF clock implementation > > * watchdog > > * uart > > * gpio > > Hi Peter, > > Heads up, in case you are not aware Arm SoC timeframes: we are at rc5, > so it means that anything targeting v6.7 should be applied this working > week, before rc6. At least as ARM SoC is concerned. Thanks for the heads up! I'm just working on v2 now incorporating all the review feedback. I'm hoping to have that sent out by the end of today or early tomorrow. Thanks, Peter.
On 10/07/2023, Krzysztof Kozlowski wrote: > On 06/10/2023 18:33, William McVicker wrote: > > On 10/06/2023, Arnd Bergmann wrote: > >> On Fri, Oct 6, 2023, at 08:06, Krzysztof Kozlowski wrote: > >>> On 06/10/2023 01:19, William McVicker wrote: > >>>> On 10/05/2023, Krzysztof Kozlowski wrote: > >>>>> On 05/10/2023 21:23, Greg KH wrote: > >>>> > >>>> Being able to include SERIAL_SAMSUNG and SERIAL_MSM without all the vendor> specific drivers that ARCH_EXYNOS and ARCH_QCOM select is very > >>> valuable for > >>>> debugging early boot issues. > >>> > >>> Really? How related? The drivers are independent. You describe some > >>> out-of-tree development process which we never needed for upstream work. > >>> And we did here quite a lot of upstream, specially if you look at ARCH_QCOM. > >> > >> Right: in general, all drivers are independent of the platform > >> besides the typical 'depends on ARCH_FOO || COMPILE_TEST' dependency, > >> but I think it's worth mentioning the known exceptions, so Greg and > >> Will can take that fight to the respective places rather than > >> discussing it in the platform submission: > >> > >> - Some subsystems are considered 'special' and the maintainers > >> prefer the drivers to be automatically selected based on the > >> ARCH_* settings instead of having user-visible options. This is > >> traditionally true for large chunks of drivers/irqchip, > >> drivers/clocksource and drivers/pinctrl, though it has gotten > >> better over time on all of them. > >> > >> - Some older 32-bit platforms are still not as modular as we'd > >> like them to be, especially the StrongARM (ARMv4) platforms that > >> require a custom kernel build, and some of ARMv4T and ARMv5 > >> boards that are still missing DT support. These tend to require > >> drivers they directly link to from board code, so disabling > >> the drivers would cause a link failure until this gets > >> cleaned up. > >> > >> - A couple of drivers are force-enabled based on the ARCH_* > >> options because booting without these drivers would risk > >> permanent damage to hardware, e.g. in overtemp or overcurrent > >> scenarios. > >> > >> - ACPI based platforms require the PCI host bridge driver to > >> be built-in rather than a loadable module because ACPI > >> needs to probe PCI devices during early boot. > >> > >> - Some subsystems (notably drivers/gpu/, but others as well) > >> have an excessive number of 'select' statements, so you > >> end up surprise-enabling a number of additional drivers > >> and subsystems by enabling certain less important platform > >> specific drivers. > >> > >> Arnd > > > > So if the argument is that the existing upstream Exynos platforms are required > > to have these drivers built-in to the kernel to boot: > > COMMON_CLK_SAMSUNG > > CLKSRC_EXYNOS_MCT > > EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS > > EXYNOS_PMU > > PINCTRL > > PINCTRL_EXYNOS > > PM_GENERIC_DOMAINS if PM > > SOC_SAMSUNG > > > > ...then that is understandable and we can work to fix that. > > > > My last question then is -- why do we need a new ARCH_GOOGLE_TENSOR config in > > the platform Kconfig? For example, I don't really like this: > > > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > > index 76a494e95027..4c8f173c4dec 100644 > > --- a/drivers/clk/samsung/Kconfig > > +++ b/drivers/clk/samsung/Kconfig > > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR > > > > What happens when we have GOOGLE_GS101_COMMON_CLK, GOOGLE_GS201_COMMON_CLK, and > > so on? > > Nothing happens... or happens anything you wish. Did you read the > motivation why this was created like this? > > > > How are we going to pick the right driver when e have a generic > > ARCH_GOOGLE_TENSOR config? > Okay, we can figure that out the gs201 specifics when the time comes. > You do not have to pick. You select ARCH_GOOGLE_TENSOR and proper pick > is done by you. Nothing to do more. > > > Ideally, we should have one Exynos clock driver that > > can detect what hardware is running (using the DT) to determine what it needs > > It's already like this. We're done. > > > to do. If you really want to compile out the other vendor's clock drivers using > > some configs, then we should do that with SOC_GS101, SOC_GS201, SOC_TESLA_FSD > > Whether you call it SOC or ARCH it is the same. We organized it as ARCH. > > > configs (not ideal though). With that approach, we could drop the platform > > ARCH_GOOGLE_TENSOR config and create an SOC_GS101 config that can be used for > > things like the COMMON_CLK_SAMSUNG driver (for now) and building the GS101 dtb. > > There is no need for this. ARCH does exactly the same. Okay, sounds good. Thanks for the responses. Regards, Will > > Best regards, > Krzysztof >
Hi folks, This series adds initial SoC support for the GS101 SoC and also initial board support for Pixel 6 phone (Oriole). The gs101 / Tensor SoC is also used in Pixel6a (bluejay) and Pixel 6 Pro (raven). Currently DT is just added for the gs101 SoC and Oriole. The support added in this series consists of: * cpus * pinctrl * some CCF clock implementation * watchdog * uart * gpio This is enough to boot through to a busybox initramfs and shell using an upstream kernel though :) More platform support will be added over the following weeks and months. Currently we boot with clk_ignore_unused parameter but this will be updated as more clocks and platform support lands. For further information on how to build and flash the upstream kernel on your Pixel 6, with a prebuilt busybox initramfs please refer to the script and README.md here: https://git.codelinaro.org/linaro/googlelt/pixelscripts I've also included the dtbo overlay containing board_id and board_rev in this series as otherwise the LK bootloader will bootloop if this is not present in the dtbo partition. It seems like it would be nicer for the upstream kernel to build all the DT required to boot upstream kernel on a production phone rather than having to obtain this dtbo from some other place, but if it is a pain point then I can remove it. Many thanks, Peter. Peter Griffin (21): dt-bindings: interrupt-controller: Add gs101 interrupt controller dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings dt-bindings: arm: google: Add bindings for Google ARM platforms dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible dt-bindings: clock: gs101: Add cmu_top clock indices dt-bindings: clock: gs101: Add cmu_apm clock indices dt-bindings: clock: gs101: Add cmu_misc clock indices clk: samsung: clk-pll: Add support for pll_{0516,0517,518} clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates clk: samsung: clk-gs101: add CMU_APM support clk: google: gs101: Add support for CMU_MISC clock unit pinctrl: samsung: Add gs101 SoC pinctrl configuration watchdog: s3c2410_wdt: Add support for Google tensor SoCs arm64: dts: google: Add initial Google gs101 SoC support google/gs101: Add dt overlay for oriole board arm64: defconfig: Enable Google Tensor SoC MAINTAINERS: add entry for Google Tensor SoC .../devicetree/bindings/arm/google.yaml | 46 + .../bindings/clock/google,gs101-clock.yaml | 109 + .../samsung,pinctrl-wakeup-interrupt.yaml | 2 + .../bindings/pinctrl/samsung,pinctrl.yaml | 4 +- .../bindings/soc/samsung/exynos-pmu.yaml | 2 + .../soc/samsung/samsung,exynos-sysreg.yaml | 7 + .../bindings/watchdog/samsung-wdt.yaml | 10 +- MAINTAINERS | 11 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 7 + arch/arm64/boot/dts/google/gs101-oriole.dts | 68 + arch/arm64/boot/dts/google/gs101-oriole.dtso | 21 + arch/arm64/boot/dts/google/gs101-pinctrl.dtsi | 1134 +++++++++ arch/arm64/boot/dts/google/gs101-pinctrl.h | 17 + arch/arm64/boot/dts/google/gs101.dtsi | 501 ++++ arch/arm64/configs/defconfig | 1 + drivers/clk/samsung/Kconfig | 9 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-gs101.c | 2171 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 9 +- drivers/clk/samsung/clk-pll.h | 3 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++ drivers/pinctrl/samsung/pinctrl-exynos.c | 68 +- drivers/pinctrl/samsung/pinctrl-exynos.h | 44 + drivers/pinctrl/samsung/pinctrl-samsung.c | 4 + drivers/pinctrl/samsung/pinctrl-samsung.h | 24 + drivers/watchdog/s3c2410_wdt.c | 116 +- include/dt-bindings/clock/gs101.h | 232 ++ .../dt-bindings/interrupt-controller/gs101.h | 758 ++++++ 30 files changed, 5533 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/google.yaml create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml create mode 100644 arch/arm64/boot/dts/google/Makefile create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dts create mode 100644 arch/arm64/boot/dts/google/gs101-oriole.dtso create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/google/gs101-pinctrl.h create mode 100644 arch/arm64/boot/dts/google/gs101.dtsi create mode 100644 drivers/clk/samsung/clk-gs101.c create mode 100644 include/dt-bindings/clock/gs101.h create mode 100644 include/dt-bindings/interrupt-controller/gs101.h