From patchwork Tue Oct 3 04:43:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 729029 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4A7165B for ; Tue, 3 Oct 2023 04:44:35 +0000 (UTC) Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D136CA4 for ; Mon, 2 Oct 2023 21:44:33 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-578b4997decso303775a12.0 for ; Mon, 02 Oct 2023 21:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696308273; x=1696913073; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=TjbE8uX71LLSwVZuJeo15FlkQKTT8tUnSt7nDx48Qbk=; b=Xclr7fO6EHMuIRyyD4enBSpvOgXY9u+6HVWCdX0sua+WLY1MxyN+N1VcxR/lOP7BEV B2E7gj14iGfePXoqYelqRLP1GSjgukd7LRarRDpf81Xp6XRp+H/yrbqQ9GnaEpXAHQ4B PkgOnqBfM59doW1GkeuS0vYyyerucT6uDVA8g+ShvVntZuubsNVAhineEon8eVQaiRvl 76S/lZGnPD62VCS94BQucJELti+l4+g4+mruyU/BzkmYJWw7c72NW8jd71RGTb81ZUMv TlwLfWYHs/KCa4cW3n0TwiR5a3bDU5RbpNn960og6Z0EpWLyCtX+0waKsOKmBE3uhWAn WR7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696308273; x=1696913073; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TjbE8uX71LLSwVZuJeo15FlkQKTT8tUnSt7nDx48Qbk=; b=G0eghDB5MaumjoXDHmncH8LigeYuoW8s1j29DU2GrCRj/jw7uA66W+BErj4lQz4xIH p522WPDa03K7epAM26ob26kNY9i9Q03bOzS8k8mo3IIQ3PfXBiP4JTh8iDtrUsOUws8+ 7XwMun69JMWzW888IkRrMRGaBOy/16KJxie5BwegJuxA5RIqG9t0XMvs3Hjttj0+HV0u S+ZxK0nE8qiQLcpTSbeeIgA0E+e4CvjDu0PWWWe/CFnzFGTH1s0ss3vr5GJcGvYSUk18 hFHgqxOVmIvq1Uur0t4OzVBchw4Xi2TzPhrwtq8+mP01bO2VdxW2Y8tLxwk9yXaXxScf 77MA== X-Gm-Message-State: AOJu0YyxK1nlFZNtZq5x3V7ydOZ4ewg+HzRlktFdBDvAgHDbUYnBTTfd B1+rNpq1tKich4IJvag3cW1SQQ== X-Google-Smtp-Source: AGHT+IFI2zSNTFfrsT7+gx7O9gi1BfXyjAK1sLcXRSVueaDfZFD28tzvs5rJ6/KTXTYGT91xnfZJpw== X-Received: by 2002:a05:6a20:430e:b0:141:d640:794a with SMTP id h14-20020a056a20430e00b00141d640794amr17673256pzk.39.1696308273182; Mon, 02 Oct 2023 21:44:33 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.132]) by smtp.gmail.com with ESMTPSA id h9-20020aa786c9000000b0068e49cb1692sm346421pfo.1.2023.10.02.21.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 21:44:32 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v10 00/15] Linux RISC-V AIA Support Date: Tue, 3 Oct 2023 10:13:48 +0530 Message-Id: <20231003044403.1974628-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The RISC-V AIA specification is ratified as-per the RISC-V international process. The latest ratified AIA specifcation can be found at: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf At a high-level, the AIA specification adds three things: 1) AIA CSRs - Improved local interrupt support 2) Incoming Message Signaled Interrupt Controller (IMSIC) - Per-HART MSI controller - Support MSI virtualization - Support IPI along with virtualization 3) Advanced Platform-Level Interrupt Controller (APLIC) - Wired interrupt controller - In MSI-mode, converts wired interrupt into MSIs (i.e. MSI generator) - In Direct-mode, injects external interrupts directly into HARTs For an overview of the AIA specification, refer the AIA virtualization talk at KVM Forum 2022: https://static.sched.com/hosted_files/kvmforum2022/a1/AIA_Virtualization_in_KVM_RISCV_final.pdf https://www.youtube.com/watch?v=r071dL8Z0yo To test this series, use QEMU v7.2 (or higher) and OpenSBI v1.2 (or higher). These patches can also be found in the riscv_aia_v10 branch at: https://github.com/avpatel/linux.git Changes since v9: - Rebased on Linux-6.6-rc4 - Use builtin_platform_driver() in PATCH5, PATCH9, and PATCH12 Changes since v8: - Rebased on Linux-6.6-rc3 - Dropped PATCH2 of v8 series since we won't be requiring riscv_get_intc_hartid() based on Marc Z's comments on ACPI AIA support. - Addressed Saravana's comments in PATCH3 of v8 series - Update PATCH9 and PATCH13 of v8 series based on comments from Sunil Changes since v7: - Rebased on Linux-6.6-rc1 - Addressed comments on PATCH1 of v7 series and split it into two PATCHes - Use DEFINE_SIMPLE_PROP() in PATCH2 of v7 series Changes since v6: - Rebased on Linux-6.5-rc4 - Updated PATCH2 to use IS_ENABLED(CONFIG_SPARC) instead of !IS_ENABLED(CONFIG_OF_IRQ) - Added new PATCH4 to fix syscore registration in PLIC driver - Update PATCH5 to convert PLIC driver into full-blown platform driver with a re-written probe function. Changes since v5: - Rebased on Linux-6.5-rc2 - Updated the overall series to ensure that only IPI, timer, and INTC drivers are probed very early whereas rest of the interrupt controllers (such as PLIC, APLIC, and IMISC) are probed as regular platform drivers. - Renamed riscv_fw_parent_hartid() to riscv_get_intc_hartid() - New PATCH1 to add fw_devlink support for msi-parent DT property - New PATCH2 to ensure all INTC suppliers are initialized which in-turn fixes the probing issue for PLIC, APLIC and IMSIC as platform driver - New PATCH3 to use platform driver probing for PLIC - Re-structured the IMSIC driver into two separate drivers: early and platform. The IMSIC early driver (PATCH7) only initialized IMSIC state and provides IPIs whereas the IMSIC platform driver (PATCH8) is probed provides MSI domain for platform devices. - Re-structure the APLIC platform driver into three separe sources: main, direct mode, and MSI mode. Changes since v4: - Rebased on Linux-6.5-rc1 - Added "Dependencies" in the APLIC bindings (PATCH6 in v4) - Dropped the PATCH6 which was changing the IOMMU DMA domain APIs - Dropped use of IOMMU DMA APIs in the IMSIC driver (PATCH4) Changes since v3: - Rebased on Linux-6.4-rc6 - Droped PATCH2 of v3 series instead we now set FWNODE_FLAG_BEST_EFFORT via IRQCHIP_DECLARE() - Extend riscv_fw_parent_hartid() to support both DT and ACPI in PATCH1 - Extend iommu_dma_compose_msi_msg() instead of adding iommu_dma_select_msi() in PATCH6 - Addressed Conor's comments in PATCH3 - Addressed Conor's and Rob's comments in PATCH7 Changes since v2: - Rebased on Linux-6.4-rc1 - Addressed Rob's comments on DT bindings patches 4 and 8. - Addessed Marc's comments on IMSIC driver PATCH5 - Replaced use of OF apis in APLIC and IMSIC drivers with FWNODE apis this makes both drivers easily portable for ACPI support. This also removes unnecessary indirection from the APLIC and IMSIC drivers. - PATCH1 is a new patch for portability with ACPI support - PATCH2 is a new patch to fix probing in APLIC drivers for APLIC-only systems. - PATCH7 is a new patch which addresses the IOMMU DMA domain issues pointed out by SiFive Changes since v1: - Rebased on Linux-6.2-rc2 - Addressed comments on IMSIC DT bindings for PATCH4 - Use raw_spin_lock_irqsave() on ids_lock for PATCH5 - Improved MMIO alignment checks in PATCH5 to allow MMIO regions with holes. - Addressed comments on APLIC DT bindings for PATCH6 - Fixed warning splat in aplic_msi_write_msg() caused by zeroed MSI message in PATCH7 - Dropped DT property riscv,slow-ipi instead will have module parameter in future. Anup Patel (15): RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs of: property: Add fw_devlink support for msi-parent drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized irqchip/sifive-plic: Fix syscore registration for multi-socket systems irqchip/sifive-plic: Convert PLIC driver into a platform driver irqchip/riscv-intc: Add support for RISC-V AIA dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller irqchip: Add RISC-V incoming MSI controller early driver irqchip/riscv-imsic: Add support for platform MSI irqdomain irqchip/riscv-imsic: Add support for PCI MSI irqdomain dt-bindings: interrupt-controller: Add RISC-V advanced PLIC irqchip: Add RISC-V advanced PLIC driver for direct-mode irqchip/riscv-aplic: Add support for MSI-mode RISC-V: Select APLIC and IMSIC drivers MAINTAINERS: Add entry for RISC-V AIA drivers .../interrupt-controller/riscv,aplic.yaml | 172 ++++++ .../interrupt-controller/riscv,imsics.yaml | 172 ++++++ MAINTAINERS | 14 + arch/riscv/Kconfig | 2 + arch/riscv/kernel/cpu.c | 11 +- drivers/irqchip/Kconfig | 24 + drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-riscv-aplic-direct.c | 343 +++++++++++ drivers/irqchip/irq-riscv-aplic-main.c | 232 +++++++ drivers/irqchip/irq-riscv-aplic-main.h | 53 ++ drivers/irqchip/irq-riscv-aplic-msi.c | 285 +++++++++ drivers/irqchip/irq-riscv-imsic-early.c | 259 ++++++++ drivers/irqchip/irq-riscv-imsic-platform.c | 319 ++++++++++ drivers/irqchip/irq-riscv-imsic-state.c | 570 ++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 67 ++ drivers/irqchip/irq-riscv-intc.c | 44 +- drivers/irqchip/irq-sifive-plic.c | 242 +++++--- drivers/of/property.c | 2 + include/linux/irqchip/riscv-aplic.h | 119 ++++ include/linux/irqchip/riscv-imsic.h | 86 +++ 20 files changed, 2915 insertions(+), 104 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h create mode 100644 drivers/irqchip/irq-riscv-aplic-msi.c create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h create mode 100644 include/linux/irqchip/riscv-aplic.h create mode 100644 include/linux/irqchip/riscv-imsic.h