From patchwork Fri Aug 25 09:12:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 717296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70563C88CB2 for ; Fri, 25 Aug 2023 09:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237035AbjHYJOB (ORCPT ); Fri, 25 Aug 2023 05:14:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238875AbjHYJNd (ORCPT ); Fri, 25 Aug 2023 05:13:33 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62FDE1FD5; Fri, 25 Aug 2023 02:13:31 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37P3uhJg027744; Fri, 25 Aug 2023 09:12:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=R6R18gHw2C5mdhOKBBzW91Z3FEvtD6d0pTm5U2bvFFw=; b=npn6LBCePTaAFrMsIQ6ABYakoFgfkE1MJu+VqZdHn26qhFDOum8p066dn3f51jABsXDF 0a1UkPP2os8S2dSB/AQ1Q0oA+QOdqqxi8Q7fHdsGtymFAnj+mswlDDgA9j2R/G9TK8zQ kCKz64wI89HfpGoCCRREAb+ObmilKnqExo3EvoXa9wFGn6gBaEwO4aTTTI4rY9RBYwDo 3UWsN8hwywmhmtSXlzoNaVEQ5NhXSoq8Q9znMzUMgj49sZQxR1VqSrKXOPjJYD1ryFUo eAMk3WOnf/1RhfxS/kJqMpvpodAoTOuB9CUypGAEtqh8vA8xwo5Y7zvby89+soewPTm2 xQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3spmtxrhb5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Aug 2023 09:12:59 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37P9CwZG029101 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Aug 2023 09:12:58 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Fri, 25 Aug 2023 02:12:51 -0700 From: Devi Priya To: , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V2 0/7] Add NSS clock controller support for IPQ9574 Date: Fri, 25 Aug 2023 14:42:27 +0530 Message-ID: <20230825091234.32713-1-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: taJa4SE5Q03McoRRGo2fYrhIPro_Xo0S X-Proofpoint-GUID: taJa4SE5Q03McoRRGo2fYrhIPro_Xo0S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-25_07,2023-08-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 spamscore=0 adultscore=0 mlxlogscore=828 mlxscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308250079 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings, driver and devicetree node for networking sub system clock controller on IPQ9574. Also add support for NSS Huayra type alpha PLL and add support for gpll0_out_aux clock which serves as the parent for some nss clocks. The NSS clock controller driver depends on the below patchset which adds support for multiple configurations for same frequency. https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/ Changes in V2: - Detailed change logs are added to the respective patches. V1 can be found at: https://lore.kernel.org/linux-arm-msm/20230711093529.18355-1-quic_devipriy@quicinc.com/ Devi Priya (7): clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-ipq9574: Add gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions clk: qcom: Add NSS clock Controller driver for IPQ9574 arm64: dts: qcom: ipq9574: Add support for nsscc node arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 107 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 12 + drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/gcc-ipq9574.c | 16 + drivers/clk/qcom/nsscc-ipq9574.c | 3109 +++++++++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 + .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 + 12 files changed, 3589 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h