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Fri, 4 Aug 2023 07:19:28 -0500 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 4 Aug 2023 07:19:25 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , , , Subject: [PATCH v8 0/2] edac: xilinx: Added EDAC support for Xilinx DDR controller Date: Fri, 4 Aug 2023 17:49:22 +0530 Message-ID: <20230804121924.18615-1-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CD:EE_|LV2PR12MB5750:EE_ X-MS-Office365-Filtering-Correlation-Id: 793dd596-10e2-44a2-ddd6-08db94e50d68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pUNSeNVH88eMryiyakI4d5FsWMEhBNJho1YHoH49S7a9jim9o+Hm8bSozjP0Bo3mMp8ULohNRigSNvVhO2AalnXhVOEdchb8k2AcSNfxowAraF7OXlPydts2dc62mKSn0o9rebMB8CRN6Zglhe6xdgU1fO4kVo8iBB4IDWT9ltEmjbjBAiITbpdGBHlp7LI8rH0flttJApywNGex8hRGHsXJp2b+2EK78cCuqlO6WWVRtcuVSn3Y0zpn02LBDz05nAENcuPXxHNNYUrNNqmD/pRKI510W8UolUIvrVv1l2fXZU8p0it1xxt3QRmpCvzPdF//5SHXLEo1DpJ4RnRf5noBfEgqdzhM0VAT5DnHYFvEs7yk22qgRSqYv2LXQYUNzvLYp5EQkVZf+D3HMGgHsnJcwvTAh+eKaY5B2mEqfmVdOYBt5Cy9rgd7MtmYtWZ+B1ep19h3NLTSOr9r7H6oobekaYK/Z4XdhvNqiqr0wtAiG17gsYAv2gumCvZ3Ee1wMggMLLL5MFzJVKXpIVt7xmvsl9Lus28yxImBKnZaO7ohoL7DlwPUWJbWt1rX1kr5T/+G+C/tIWPyKelLzDAUXIMCx1ULPimyTUjh9cvGlr3YnEsTVGW6+hGmZkld5gZosUg/65J3RnwTBynPIyY8AZh4ebnBUta/0j2L2qxUiPmRPP/dx9qxWm1Fvxrkfnzgr52z3IcZHhOxbHR+bnabSA1onLk0YAIBfzaVbYu1n1gI/PL8nmLb5a84FRuh+3T7jcmSZAOSml9Hh7kNzO6l4w== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(39860400002)(346002)(376002)(136003)(82310400008)(451199021)(1800799003)(186006)(36840700001)(40470700004)(46966006)(2906002)(1076003)(336012)(26005)(81166007)(356005)(82740400003)(2616005)(36860700001)(47076005)(40480700001)(426003)(83380400001)(44832011)(5660300002)(7416002)(8676002)(8936002)(70206006)(70586007)(4326008)(6916009)(316002)(41300700001)(36756003)(40460700003)(6666004)(86362001)(54906003)(478600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2023 12:19:29.5830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 793dd596-10e2-44a2-ddd6-08db94e50d68 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5750 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/4X memory interfaces. It has four programmable NoC interface ports and is designed to handle multiple streams of traffic. Optional external interface reliability include ECC error detection/correction and command address parity. Adding edac support for DDR Memory controller. Changes in v8: remove disabling all interrupts Changes in v7: Update the subject to add memory-controllers instead of edac Update the message Clear status after handling the error At probe disable all the unrequested interrupts. Alphabetically sorted diff Rename unCorrectable to uncorrectable Use mask0 for GENMASK(0,5) Add a processbit function Changes in v6: Fix the warn. Changes in v5: Update subject Changes in v4: Update the reviewed by tag Update the subject rename the driver file. fix the debugfs file. fix unneeded capitalisation. refactor code Changes in v3: Rebased and resent. Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names Update a missed out file remove edac from compatible name rename ddrmc_noc_base and ddrmc_base Shubhrajyoti Datta (2): dt-bindings: memory-controllers: Add support for Xilinx Versal EDAC for DDRMC EDAC/versal: Add a Xilinx Versal memory controller driver .../xlnx,versal-ddrmc-edac.yaml | 57 + MAINTAINERS | 7 + drivers/edac/Kconfig | 11 + drivers/edac/Makefile | 1 + drivers/edac/versal_edac.c | 1065 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 12 + 6 files changed, 1153 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml create mode 100644 drivers/edac/versal_edac.c