From patchwork Fri Aug 4 02:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 710744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 910D1C00528 for ; Fri, 4 Aug 2023 02:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232790AbjHDCDE convert rfc822-to-8bit (ORCPT ); Thu, 3 Aug 2023 22:03:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231465AbjHDCDD (ORCPT ); Thu, 3 Aug 2023 22:03:03 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4F1A4488; Thu, 3 Aug 2023 19:02:57 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 112398067; Fri, 4 Aug 2023 10:02:56 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:56 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 4 Aug 2023 10:02:55 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v6 0/3] Add initialization of clock for StarFive JH7110 SoC Date: Fri, 4 Aug 2023 10:02:51 +0800 Message-ID: <20230804020254.291239-1-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series. Changes v5->v4: - Rebased to v6.4rc4. - Dropped the Reported-by tags. Changes v4->v5: - Rebased to v6.5rc2. - Changed the way to initialization the clocks. - Changed the layout for the SPI flash. Changes v3->v4: - Added minItems for clocks. - Added clock names property. - Fixed formatting issues. Changes v2->v3: - Rebased to v6.4rc6. - Renamed the clock names. - Changed the variable definition type. Changes v1->v2: - Renamed the clock names. - Specified a different array of clocks. - Used clk_bulk_ APIs. The patch series is based on v6.5rc4. William Qiu (3): dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC .../bindings/spi/cdns,qspi-nor.yaml | 12 +++- .../jh7110-starfive-visionfive-2.dtsi | 36 ++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 19 ++++++ drivers/spi/spi-cadence-quadspi.c | 67 +++++++++++++++++++ 4 files changed, 133 insertions(+), 1 deletion(-) --- 2.34.1