From patchwork Thu Jul 13 12:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 702395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A710C0015E for ; Thu, 13 Jul 2023 12:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232646AbjGMMMc (ORCPT ); Thu, 13 Jul 2023 08:12:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230027AbjGMMMb (ORCPT ); Thu, 13 Jul 2023 08:12:31 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDE741FEA; Thu, 13 Jul 2023 05:12:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250350; x=1720786350; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=/7sS6FP9LTjC31OWZxS14sLk//bNWTQVsuYQYTG9dS4=; b=DnI/eJ5RzY2w1/VU/kCc9ht0VPWaiJWrkqeoXZHiTtVCMcyD7Ji4Ro6R Uu7XWEtz3ls0R0vS4BFLTkGRNrFtuauN4+/M/7IA6e0ubtgw3tI2lJJXW YZwRIwCeoQwcmYzq7MhNX2uMANKG3U+qNoo+kmxCTaPQTRmJTiy5m0HlM lAHPsg3/81kreSe/wyVZdUBcrSwQyp8+ZoCoAxFphL47obF4W5REF/ryg R1+XkhBDU0QGOyJp0hCrqwqlToDrrPWEocn7SNPdzzUvE16p/kpr4zHXt Twct068Ibvtou1S2X8hXGUuj0/jIjmfj4UWshaQI6TuuCjlP9gsLxN/IM A==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="235310965" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:29 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:27 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Date: Thu, 13 Jul 2023 13:10:58 +0100 Message-ID: <20230713-target-much-8ac624e90df8@wendy> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3429; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=/7sS6FP9LTjC31OWZxS14sLk//bNWTQVsuYQYTG9dS4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX175KZUvprYw7LniWt4b7+0LnfYGL9z3rG7qy0xPrQe5 xXO5O0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjAR8UyGfyodqTXq87O25KUlLuC+zX dsglTF/H0KC0rkFoTfum/5LJ7hn56m/Nn7T22eh0XbJ1w48HBPoLvgaa3X1lpz50y8dDEyiBsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hey, Based on my latest iteration of deprecating riscv,isa [1], here's an implementation of the new properties for Linux. The first few patches, up to "RISC-V: split riscv_fill_hwcap() in 3", are all prep work that further tames some of the extension related code, on top of my already applied series that cleans up the ISA string parser. Perhaps "RISC-V: shunt isa_ext_arr to cpufeature.c" is a bit gratuitous, but I figured a bit of coalescing of extension related data structures would be a good idea. Note that riscv,isa will still be used in the absence of the new properties. Palmer suggested adding a Kconfig option to turn off the fallback for DT, which I have gone and done. It's locked behind the NONPORTABLE option for good reason. In v2, I've also come up with a more reasonable name for the new function I added & fixed up various comments from Drew and Evan. In v3, there's the new commandline option that Drew suggested. I have Also picked up a patch from Palmer that adds more helpful prints where harts fail the checks in riscv_early_of_processor_id(), and I've sprinkled a few more of those prints in my new additions to the function. v4 just rebases on v6.5-rc1 and fixes the nommu build issue due to a missing __init. In v5, I've fixed issues spotted by myself & Evan. I'm not the worlds biggest fan of the strlen() calls inside the macro - but that's going to go away again almost immediately if the scalar crypto stuff gets merged. I also spotted an issue with a rebase I did at some point, where the dedicated properties did not use isainfo->isa & created a bitmap for each cpu, which would've caused the per-hart extension tracking to break. Cheers, Conor. [1] (it's in v6.5-rc1 now) CC: Rob Herring CC: Krzysztof Kozlowski CC: Paul Walmsley CC: Palmer Dabbelt CC: Albert Ou CC: Jonathan Corbet CC: Andrew Jones CC: Heiko Stuebner CC: Evan Green CC: Sunil V L CC: linux-doc@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org Conor Dooley (9): RISC-V: drop a needless check in print_isa_ext() RISC-V: shunt isa_ext_arr to cpufeature.c RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() RISC-V: add missing single letter extension definitions RISC-V: add single letter extensions to riscv_isa_ext RISC-V: split riscv_fill_hwcap() in 3 RISC-V: enable extension detection from dedicated properties RISC-V: try new extension properties in of_early_processor_hartid() RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Heiko Stuebner (1): RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Palmer Dabbelt (1): RISC-V: Provide a more helpful error message on invalid ISA strings .../admin-guide/kernel-parameters.txt | 7 + arch/riscv/Kconfig | 18 + arch/riscv/include/asm/hwcap.h | 17 +- arch/riscv/kernel/cpu.c | 179 +++--- arch/riscv/kernel/cpufeature.c | 521 ++++++++++++------ 5 files changed, 439 insertions(+), 303 deletions(-)