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Sun, 25 Jun 2023 05:02:57 -0500 Received: from xhdakumarma40u.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Sun, 25 Jun 2023 05:02:53 -0500 From: Amit Kumar Mahapatra To: , , , , , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v3 0/2] mtd: spi-nor: Avoid setting SRWD bit in SR Date: Sun, 25 Jun 2023 15:32:49 +0530 Message-ID: <20230625100251.31589-1-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT088:EE_|CH3PR12MB8209:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e55133c-c0a2-463e-1ba5-08db75635abb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cK/5wfxhz6sZyxb0BDY+f5yA9aNhIVlWu5fnXE9KtmXSQynirNbrGE7cH4dyQ4gKX/ccx9QTrCuO+ojNt2HXjPhZPKYtLtd5IVkWu4JjEhCttWEo1B+tuvZqFCtwFlyO+A9BkSvsFj+2C8HsuT0F8b5mTU0HKgwosziXnBNpPn/m/98rwR9f9Z2zM8CdVG89rDEbKoGu3kEiz0uOjlb1FWZNtg3bhI2TQDLCNMzQiNLEXHmv90K0b0khz1YLgV+szOlr6xk7EkSZznKlBCkFc4suLkFRWjkkhzQrRreK0e+7kmWUcYOPPnjLWa4GjLIUjREYXWTfr6DkRAdUDNUQr934vspjSdEzFNzoU9K6b4P06p3gE8+rhm6Mm3AC/zoVkfTVYiy+sqnNXNLlfCKHA3XW+stCqJVPY+vkHn3VIDstoNJqhb3zcNmkyd2xvH603UZTaAFW3Tc10VGCLxPj3Wb2bcM+PRuvyYlVaZ6P849Q2OQFvgEOUaCMgXt3uO5/O5ldGv4eGbkK9XcBc3WwBq3y8iVxaiV2LhOLRmSDw1zOs3d3EdTgq6XwqaGdVnWJFgtt9BO8mOuBhESuxGF7XxUK4pztgHahmCz2sniZcihhAwXrHM38+bLx+02nMBGgVv50d9PCim/3IXR3yPsrNryeujJCeCQD+4cWzzcbK2+25BYJPdt6sqxCtFwbRdLwy0jtY0rbg3VmgJ9thMuZ8Rdy8DZ5me+fLnxBC2t7TacJI+ZcYrFaDvc1O6dEtSaGWd8IVwrs/8+pKPezW1aX2g== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(82310400005)(186003)(26005)(2906002)(82740400003)(6666004)(7416002)(8676002)(36756003)(316002)(54906003)(478600001)(86362001)(110136005)(4326008)(47076005)(2616005)(81166007)(336012)(426003)(1076003)(41300700001)(40460700003)(5660300002)(8936002)(83380400001)(70586007)(70206006)(356005)(36860700001)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2023 10:02:58.6699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e55133c-c0a2-463e-1ba5-08db75635abb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8209 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash not connected or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. To avoid this a boolean type DT property "no-wp" is introduced. If this property is defined, the spi-nor doesn't set the SRWD bit in SR while performing flash protection operation. Reviewed-by: Conor Dooley --- BRANCH: for-next Changes in v3: - Updated DT property name to "no-wp". - Removed Reviewed-by tag from 1/2 as the DT property name has changed. - Updated spi-nor flag name to SNOR_F_NO_WP. - Updated DT property description. - Updated patch description. - Updated comments in swp.c file. - Replaced WP with WP# in patch descriptions, comments & DT property description. Changes in v2: - Modified DT property description to add information about a valid use case. - Added Reviewed-by tag in 1/2. - Updated comment description in 2/2. --- Amit Kumar Mahapatra (2): dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 4 files changed, 26 insertions(+), 2 deletions(-)