| Message ID | 20230625100251.31589-1-amit.kumar-mahapatra@amd.com |
|---|---|
| Headers | show |
| Series | mtd: spi-nor: Avoid setting SRWD bit in SR | expand |
On Sun, Jun 25, 2023 at 03:32:50PM +0530, Amit Kumar Mahapatra wrote: > If the WP# signal of the flash device is either not connected or is wrongly > tied to GND (that includes internal pull-downs), and the software sets the > status register write disable (SRWD) bit in the status register then the > status register permanently becomes read-only. To avoid this added a new > boolean DT property "no-wp". If this property is set in the DT then the > software avoids setting the SRWD during status register write operation. > > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> > --- > As the DT property name has changed so, removed Reviewed-by tag. > @Cornor if possible, could you please review this updated patch. Rob was the one who objected to the property name. Old & new names are fine by me, it was the text I think I cared about. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks for actually explaining why you dropped the tag, Conor. > --- > .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > index 89959e5c47ba..97344969b02d 100644 > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml > @@ -70,6 +70,21 @@ properties: > be used on such systems, to denote the absence of a reliable reset > mechanism. > > + no-wp: > + type: boolean > + description: > + The status register write disable (SRWD) bit in status register, combined > + with the WP# signal, provides hardware data protection for the device. When > + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard > + strapped to LOW, the status register nonvolatile bits become read-only and > + the WRITE STATUS REGISTER operation will not execute. The only way to exit > + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the > + flash device is not connected or is wrongly tied to GND (that includes internal > + pull-downs) then status register permanently becomes read-only as the SRWD bit > + cannot be reset. This boolean flag can be used on such systems to avoid setting > + the SRWD bit while writing the status register. WP# signal hard strapped to GND > + can be a valid use case. > + > reset-gpios: > description: > A GPIO line connected to the RESET (active low) signal of the device. > -- > 2.17.1 >
Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash not connected or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. To avoid this a boolean type DT property "no-wp" is introduced. If this property is defined, the spi-nor doesn't set the SRWD bit in SR while performing flash protection operation. --- BRANCH: for-next Changes in v3: - Updated DT property name to "no-wp". - Removed Reviewed-by tag from 1/2 as the DT property name has changed. - Updated spi-nor flag name to SNOR_F_NO_WP. - Updated DT property description. - Updated patch description. - Updated comments in swp.c file. - Replaced WP with WP# in patch descriptions, comments & DT property description. Changes in v2: - Modified DT property description to add information about a valid use case. - Added Reviewed-by tag in 1/2. - Updated comment description in 2/2. --- Amit Kumar Mahapatra (2): dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 4 files changed, 26 insertions(+), 2 deletions(-)