| Message ID | 20230616170022.76107-1-sebastian.reichel@collabora.com |
|---|---|
| Headers | show |
| Series | RK3588 PCIe2 support | expand |
Hi Sebastian On Fri, Jun 16, 2023 at 07:00:18PM +0200, Sebastian Reichel wrote: > Hi, > > This adds PCIe2 support for RK3588. The series has been tested with the > onboard RTL8125 network card on Rockchip RK3588 EVB1 (&pcie2x1l1) and > Radxa Rock 5B (&pcie2x1l2). The final patch in this series depends on > the combo PHY support added by the SATA series [0]. Thanks for submitting the patchset. I'll have a closer look at it on the next week. -Sergey(y) > > [0] https://lore.kernel.org/all/20230612171337.74576-1-sebastian.reichel@collabora.com/ > > Thanks, > > -- Sebastian > > Sebastian Reichel (4): > dt-bindings: PCI: dwc: rockchip: Fix interrupt-names issue > dt-bindings: PCI: dwc: rockchip: Add missing > legacy-interrupt-controller > dt-bindings: PCI: dwc: rockchip: Update for RK3588 > arm64: dts: rockchip: rk3588: add PCIe2 support > > .../bindings/pci/rockchip-dw-pcie.yaml | 58 +++++++++- > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 54 +++++++++ > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 108 ++++++++++++++++++ > 4 files changed, 231 insertions(+), 4 deletions(-) > > -- > 2.39.2 >
Hi Sebastian, On 2023-06-16 19:00, Sebastian Reichel wrote: > Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 > also has two PCIe3 IP blocks, that will be handled separately. > > Co-developed-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 54 +++++++++++ > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 108 ++++++++++++++++++++++ > 2 files changed, 162 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > index b9508cea34f1..40fee1367b34 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > @@ -80,6 +80,60 @@ i2s10_8ch: i2s@fde00000 { > status = "disabled"; > }; > > + pcie2x1l0: pcie@fe170000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x20 0x2f>; > + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, > + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, > + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, > + <0 0 0 2 &pcie2x1l0_intc 1>, > + <0 0 0 3 &pcie2x1l0_intc 2>, > + <0 0 0 4 &pcie2x1l0_intc 3>; > + linux,pci-domain = <2>; > + num-ib-windows = <8>; > + num-ob-windows = <8>; > + num-viewport = <4>; > + max-link-speed = <2>; > + msi-map = <0x2000 &its0 0x2000 0x1000>; > + num-lanes = <1>; > + phys = <&combphy1_ps PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, > + <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; For the RK356x [1] and for RK3588 in u-boot [2] the pci_addr range was changed to be in 32-bit address space, start address at 0x40000000, to make the 1 GB region available for 32-bit BARs. Something that possible could/should be done here too? E.g.: <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000> [1] https://lore.kernel.org/all/20230601132516.153934-1-frattaroli.nicolas@gmail.com/ [2] https://lore.kernel.org/u-boot/20230517100102.109855-1-eugen.hristev@collabora.com/ > + reg = <0xa 0x40800000 0x0 0x00400000>, > + <0x0 0xfe170000 0x0 0x00010000>, > + <0x0 0xf2000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; > + reset-names = "pwr", "pipe"; > + status = "disabled"; > + > + pcie2x1l0_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > gmac0: ethernet@fe1b0000 { > compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; > reg = <0x0 0xfe1b0000 0x0 0x10000>; > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > index a73b17f597af..b5fdc046d8f7 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > @@ -1670,6 +1670,114 @@ qos_vop_m1: qos@fdf82200 { > reg = <0x0 0xfdf82200 0x0 0x20>; > }; > > + pcie2x1l1: pcie@fe180000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x30 0x3f>; > + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, > + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, > + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, > + <0 0 0 2 &pcie2x1l1_intc 1>, > + <0 0 0 3 &pcie2x1l1_intc 2>, > + <0 0 0 4 &pcie2x1l1_intc 3>; > + linux,pci-domain = <3>; > + num-ib-windows = <8>; > + num-ob-windows = <8>; > + num-viewport = <4>; > + max-link-speed = <2>; > + msi-map = <0x3000 &its0 0x3000 0x1000>; > + num-lanes = <1>; > + phys = <&combphy2_psu PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, > + <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; And: <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000> > + reg = <0xa 0x40c00000 0x0 0x00400000>, > + <0x0 0xfe180000 0x0 0x00010000>, > + <0x0 0xf3000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; > + reset-names = "pwr", "pipe"; > + status = "disabled"; > + > + pcie2x1l1_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > + pcie2x1l2: pcie@fe190000 { > + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + bus-range = <0x40 0x4f>; > + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, > + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, > + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe"; > + device_type = "pci"; > + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, > + <0 0 0 2 &pcie2x1l2_intc 1>, > + <0 0 0 3 &pcie2x1l2_intc 2>, > + <0 0 0 4 &pcie2x1l2_intc 3>; > + linux,pci-domain = <4>; > + num-ib-windows = <8>; > + num-ob-windows = <8>; > + num-viewport = <4>; > + max-link-speed = <2>; > + msi-map = <0x4000 &its0 0x4000 0x1000>; > + num-lanes = <1>; > + phys = <&combphy0_ps PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + power-domains = <&power RK3588_PD_PCIE>; > + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, > + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, > + <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; And: <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000> Regards, Jonas > + reg = <0xa 0x41000000 0x0 0x00400000>, > + <0x0 0xfe190000 0x0 0x00010000>, > + <0x0 0xf4000000 0x0 0x00100000>; > + reg-names = "dbi", "apb", "config"; > + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; > + reset-names = "pwr", "pipe"; > + status = "disabled"; > + > + pcie2x1l2_intc: legacy-interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; > + }; > + }; > + > gmac1: ethernet@fe1c0000 { > compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; > reg = <0x0 0xfe1c0000 0x0 0x10000>;
On Fri, 16 Jun 2023 19:00:19 +0200, Sebastian Reichel wrote: > The RK356x (and RK3588) have 5 ganged interrupts. For example the > "legacy" interrupt combines "inta/intb/intc/intd" with a register > providing the details. > > Currently the binding is not specifying these interrupts resulting > in a bunch of errors for all rk356x boards using PCIe. > > Fix this by specifying the interrupts and add them to the example > to prevent regressions. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > .../bindings/pci/rockchip-dw-pcie.yaml | 18 ++++++++++++++++++ > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++++++++++++++- > 2 files changed, 32 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Fri, Jun 16, 2023 at 07:00:18PM +0200, Sebastian Reichel wrote: > Hi, > > This adds PCIe2 support for RK3588. The series has been tested with the > onboard RTL8125 network card on Rockchip RK3588 EVB1 (&pcie2x1l1) and > Radxa Rock 5B (&pcie2x1l2). The final patch in this series depends on > the combo PHY support added by the SATA series [0]. > > [0] https://lore.kernel.org/all/20230612171337.74576-1-sebastian.reichel@collabora.com/ > > Thanks, > > -- Sebastian > > Sebastian Reichel (4): > dt-bindings: PCI: dwc: rockchip: Fix interrupt-names issue > dt-bindings: PCI: dwc: rockchip: Add missing > legacy-interrupt-controller > dt-bindings: PCI: dwc: rockchip: Update for RK3588 > arm64: dts: rockchip: rk3588: add PCIe2 support I applied patches 1-3. Rob
On Tue, Jun 27, 2023 at 07:48:29AM -0600, Rob Herring wrote: > On Tue, Jun 27, 2023 at 6:27 AM Serge Semin <fancer.lancer@gmail.com> wrote: > > > > On Fri, Jun 16, 2023 at 07:00:19PM +0200, Sebastian Reichel wrote: > > > The RK356x (and RK3588) have 5 ganged interrupts. For example the > > > "legacy" interrupt combines "inta/intb/intc/intd" with a register > > > providing the details. > > > > > > Currently the binding is not specifying these interrupts resulting > > > in a bunch of errors for all rk356x boards using PCIe. > > > > > > Fix this by specifying the interrupts and add them to the example > > > to prevent regressions. > > > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > > --- > > > .../bindings/pci/rockchip-dw-pcie.yaml | 18 ++++++++++++++++++ > > > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++++++++++++++- > > > 2 files changed, 32 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > index 24c88942e59e..98e45d2d8dfe 100644 > > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > @@ -56,6 +56,17 @@ properties: > > > - const: pclk > > > - const: aux > > > > > > + interrupts: > > > + maxItems: 5 > > > + > > > + interrupt-names: > > > + items: > > > + - const: sys > > > + - const: pmc > > > + - const: msg > > > + - const: legacy > > > + - const: err > > > + > > > msi-map: true > > > > > > num-lanes: true > > > @@ -98,6 +109,7 @@ unevaluatedProperties: false > > > > > > examples: > > > - | > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > > > > bus { > > > #address-cells = <2>; > > > @@ -117,6 +129,12 @@ examples: > > > "aclk_dbi", "pclk", > > > "aux"; > > > device_type = "pci"; > > > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > > > linux,pci-domain = <2>; > > > max-link-speed = <2>; > > > msi-map = <0x2000 &its 0x2000 0x1000>; > > > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > > index 1a83f0f65f19..9f605eb297f5 100644 > > > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > > @@ -193,9 +193,22 @@ properties: > > > oneOf: > > > - description: See native "app" IRQ for details > > > enum: [ intr ] > > > > The IRQs below are either combined version of the already defined IRQs > > or just the generic DW PCIe IRQs but named differently. Moreover I > > don't see kernel using any of them except the "legacy" interrupt. What > > about converting the dts files to using the already defined names instead > > of extending the already over-diverged DT-bindings? > > Rob, Krzysztof? > > If there's not a dependency on the names, then we can get away with > changing them. Otherwise, it's an ABI issue to change them. Supporting > both names in the driver partially mitigates that, but isn't worth > carrying that IMO. DW Rockchip LLDD only looks for the "legacy" IRQ name. The rest of them are left unused by both LLDD and the DW PCIe core driver. So from the kernel point of view ABI is defined for "legacy" name only. Even "msi"/"msg" IRQ name left unused which is normally responsible for signaling MSI TLPs caught by the iMSI-RX engine. (Most likely MSI packets passes through the PCI<->System bus bridge and gets detected by the system GIC.) -Serge(y) > > Will drop this one from my tree. Seems patches 2 and 3 aren't > dependent on this one. > > Rob
Hi, Sorry for the delayed response. On Tue, Jun 27, 2023 at 03:27:33PM +0300, Serge Semin wrote: > On Fri, Jun 16, 2023 at 07:00:19PM +0200, Sebastian Reichel wrote: > > The RK356x (and RK3588) have 5 ganged interrupts. For example the > > "legacy" interrupt combines "inta/intb/intc/intd" with a register > > providing the details. > > > > Currently the binding is not specifying these interrupts resulting > > in a bunch of errors for all rk356x boards using PCIe. > > > > Fix this by specifying the interrupts and add them to the example > > to prevent regressions. > > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > --- > > .../bindings/pci/rockchip-dw-pcie.yaml | 18 ++++++++++++++++++ > > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++++++++++++++- > > 2 files changed, 32 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > index 24c88942e59e..98e45d2d8dfe 100644 > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > @@ -56,6 +56,17 @@ properties: > > - const: pclk > > - const: aux > > > > + interrupts: > > + maxItems: 5 > > + > > + interrupt-names: > > + items: > > + - const: sys > > + - const: pmc > > + - const: msg > > + - const: legacy > > + - const: err > > + > > msi-map: true > > > > num-lanes: true > > @@ -98,6 +109,7 @@ unevaluatedProperties: false > > > > examples: > > - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > > bus { > > #address-cells = <2>; > > @@ -117,6 +129,12 @@ examples: > > "aclk_dbi", "pclk", > > "aux"; > > device_type = "pci"; > > + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; > > linux,pci-domain = <2>; > > max-link-speed = <2>; > > msi-map = <0x2000 &its 0x2000 0x1000>; > > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > index 1a83f0f65f19..9f605eb297f5 100644 > > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml > > @@ -193,9 +193,22 @@ properties: > > oneOf: > > - description: See native "app" IRQ for details > > enum: [ intr ] > > The IRQs below are either combined version of the already defined IRQs > or just the generic DW PCIe IRQs but named differently. Moreover I > don't see kernel using any of them except the "legacy" interrupt. What > about converting the dts files to using the already defined names instead > of extending the already over-diverged DT-bindings? > Rob, Krzysztof? > > In anyway in order to prevent from defining the new DW PCIe bindings > compatible with your vendor-specific names please move the aliases to > being under the last entry of the "interrupt-names" items property. > (See the "intr" IRQ name for example or the way the vendor-specific > names are defined in the reg-names property.) All of these are combined interrupts and not simple aliases. Otherwise I would just have changed the name for RK3588. Rockchip has a two level interrupt system. I re-checked carefully and as far as I can tell all interrupts currently defined in the binding have a specific meaning. This is not the case for the interrupts from RK3588. I will send a new version in a jiffy, which describes all the sub-IRQs available beneath the newly described ones. I don't have the Synopsys datasheet, so I will stick to the names used by Rockchip. > > + - description: Combined Legacy A/B/C/D interrupt signal. > > + const: legacy > > This is a combined signal of "^int(a|b|c|d)$". So the entry > is supposed to look: > + - description: See native "int*" IRQ for details > + const: legacy In case my explanation from above was not clear: All the other interrupts follow the same style as this one. > > + - description: Combined System interrupt signal. > > + const: sys > > This seems like the "app" interrupt. So please either convert the dts > file to using the "app" name or move this to being defined in the same > entry as the "intr" name. I suppose "sys", "pmc", "msg" and "err" all fit for "app", since they are vendor specific with the extra layer? But obviously I cannot specify "app" more than once. > > + - description: Combined Power Management interrupt signal. > > + const: pmc > > This is an alias to the already defined "pme" name. So either convert > the dts file to using "pme" or move this to being in the > vendor-specific list of the "interrupt-names" property: > + - description: See native "pme" IRQ for details > + const: pmc pme should be 'msg -> pm_pme_int': Interrupt indicates that the controller received a PM_PME message. > > + - description: Combined Message Received interrupt signal. > > + const: msg > > ditto but with respect to the "msi" name. MSI is handled via GIC-ITS using this DT property: msi-map = <0x3000 &its0 0x3000 0x1000>; > > + - description: Combined Error interrupt signal. > > + const: err > > ditto but with respect to the "sft_*" name. I really meant it, when I wrote "Combined". Appart from (un)correctable errors this also reports e.g. timeouts. > > + > > allOf: > > - contains: > > - const: msi > > + enum: > > + - msi > > + - msg > > * Please see my suggestion about converting the DTS file instead. My understanding is, that "msi" and "msg" are not the same. MSI is an interrupt message from a peripheral device, but "msg" is a combined interrupt for all kind of messages. -- Sebastian
Hi, This adds PCIe2 support for RK3588. The series has been tested with the onboard RTL8125 network card on Rockchip RK3588 EVB1 (&pcie2x1l1) and Radxa Rock 5B (&pcie2x1l2). The final patch in this series depends on the combo PHY support added by the SATA series [0]. [0] https://lore.kernel.org/all/20230612171337.74576-1-sebastian.reichel@collabora.com/ Thanks, -- Sebastian Sebastian Reichel (4): dt-bindings: PCI: dwc: rockchip: Fix interrupt-names issue dt-bindings: PCI: dwc: rockchip: Add missing legacy-interrupt-controller dt-bindings: PCI: dwc: rockchip: Update for RK3588 arm64: dts: rockchip: rk3588: add PCIe2 support .../bindings/pci/rockchip-dw-pcie.yaml | 58 +++++++++- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 54 +++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 108 ++++++++++++++++++ 4 files changed, 231 insertions(+), 4 deletions(-)