mbox series

[0/3] Add R5F and C7x DSP nodes for J721S2 SoC.

Message ID 20230529220941.10801-1-hnagalla@ti.com
Headers show
Series Add R5F and C7x DSP nodes for J721S2 SoC. | expand

Message

Hari Nagalla May 29, 2023, 10:09 p.m. UTC
This series adds the R5F processor nodes and C7x DSP nodes for 
J721S2 SoC.

The first two patches adds the remote proc nodes to the SoC device
tree and the third patch reserves the memory for remote proc IPCs
on J721S2 EVM board.

Hari Nagalla (3):
  arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor
    nodes
  arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes
  arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for
    R5F and C71x DSPs

 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi    | 128 ++++++--
 .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi     |  40 +++
 arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi  | 286 ++++++++++++++++++
 3 files changed, 430 insertions(+), 24 deletions(-)

Comments

Nishanth Menon June 1, 2023, 1:27 p.m. UTC | #1
On 17:09-20230529, Hari Nagalla wrote:
> The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
> subsystems/clusters in MAIN voltage domain. Each of these can be
> configured at boot time to be either run in a LockStep mode or in an
> Asymmetric Multi Processing (AMP) fashion in Split-mode. These
> subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
> memories for each core split between two banks - ATCM and BTCM
> (further interleaved into two banks). The TCMs of both Cores are
> combined in LockStep-mode to provide a larger 128 KB of memory, but
> otherwise are functionally similar to those on J721E SoCs.
> 
> Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two
> R5F cores are added as child nodes to each of the R5F cluster nodes.
> The clusters are configured to run in LockStep mode by default, with
> the ATCMs enabled to allow the R5 cores to execute code from DDR
> with boot-strapping code from ATCM. The inter-processor communication
> between the main A72 cores and these processors is achieved through
> shared memory and Mailboxes.
> 
> The following firmware names are used by default for these cores, and
> can be overridden in a board dts file if desired:
>         MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes)
>         MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode)
>         MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes)
>         MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode)
> 
> The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The
> C71x DSPs are 64 bit machine with fixed and floating point DSP operations.
> Similar to the R5F remote cores, the inter-processor communication
> between the main A72 cores and these DSP cores is achieved through
> shared memory and Mailboxes.
> 
> The following firmware names are used by default for these DSP cores,
> and can be overridden in a board dts file if desired:
>         MAIN C71_0 : j721s2-c71_0-fw
>         MAIN C71_1 : j721s2-c71_1-fw
> 
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 128 +++++++++++++++++----
>  1 file changed, 104 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 2dd7865f7654..361aa6b24b22 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -463,7 +463,6 @@ mailbox0_cluster0: mailbox@31f80000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";

See https://lore.kernel.org/all/20221020160305.18711-9-afd@ti.com/
NAK.
>  		};
>  
>  		mailbox0_cluster1: mailbox@31f81000 {
> @@ -473,7 +472,6 @@ mailbox0_cluster1: mailbox@31f81000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster2: mailbox@31f82000 {
> @@ -483,7 +481,6 @@ mailbox0_cluster2: mailbox@31f82000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster3: mailbox@31f83000 {
> @@ -493,7 +490,6 @@ mailbox0_cluster3: mailbox@31f83000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster4: mailbox@31f84000 {
> @@ -503,7 +499,6 @@ mailbox0_cluster4: mailbox@31f84000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster5: mailbox@31f85000 {
> @@ -513,7 +508,6 @@ mailbox0_cluster5: mailbox@31f85000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster6: mailbox@31f86000 {
> @@ -523,7 +517,6 @@ mailbox0_cluster6: mailbox@31f86000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster7: mailbox@31f87000 {
> @@ -533,7 +526,6 @@ mailbox0_cluster7: mailbox@31f87000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster8: mailbox@31f88000 {
> @@ -543,7 +535,6 @@ mailbox0_cluster8: mailbox@31f88000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster9: mailbox@31f89000 {
> @@ -553,7 +544,6 @@ mailbox0_cluster9: mailbox@31f89000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster10: mailbox@31f8a000 {
> @@ -563,7 +553,6 @@ mailbox0_cluster10: mailbox@31f8a000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox0_cluster11: mailbox@31f8b000 {
> @@ -573,7 +562,6 @@ mailbox0_cluster11: mailbox@31f8b000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster0: mailbox@31f90000 {
> @@ -583,7 +571,6 @@ mailbox1_cluster0: mailbox@31f90000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster1: mailbox@31f91000 {
> @@ -593,7 +580,6 @@ mailbox1_cluster1: mailbox@31f91000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster2: mailbox@31f92000 {
> @@ -603,7 +589,6 @@ mailbox1_cluster2: mailbox@31f92000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster3: mailbox@31f93000 {
> @@ -613,7 +598,6 @@ mailbox1_cluster3: mailbox@31f93000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster4: mailbox@31f94000 {
> @@ -623,7 +607,6 @@ mailbox1_cluster4: mailbox@31f94000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster5: mailbox@31f95000 {
> @@ -633,7 +616,6 @@ mailbox1_cluster5: mailbox@31f95000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster6: mailbox@31f96000 {
> @@ -643,7 +625,6 @@ mailbox1_cluster6: mailbox@31f96000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster7: mailbox@31f97000 {
> @@ -653,7 +634,6 @@ mailbox1_cluster7: mailbox@31f97000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster8: mailbox@31f98000 {
> @@ -663,7 +643,6 @@ mailbox1_cluster8: mailbox@31f98000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster9: mailbox@31f99000 {
> @@ -673,7 +652,6 @@ mailbox1_cluster9: mailbox@31f99000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster10: mailbox@31f9a000 {
> @@ -683,7 +661,6 @@ mailbox1_cluster10: mailbox@31f9a000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		mailbox1_cluster11: mailbox@31f9b000 {
> @@ -693,7 +670,6 @@ mailbox1_cluster11: mailbox@31f9b000 {
>  			ti,mbox-num-users = <4>;
>  			ti,mbox-num-fifos = <16>;
>  			interrupt-parent = <&main_navss_intr>;
> -			status = "disabled";
>  		};
>  
>  		main_ringacc: ringacc@3c000000 {
> @@ -1102,4 +1078,108 @@ main_spi7: spi@2170000 {
>  		clocks = <&k3_clks 346 1>;
>  		status = "disabled";
>  	};
> +
> +	main_r5fss0: r5fss@5c00000 {
> +		compatible = "ti,j721s2-r5fss";
> +		ti,cluster-mode = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
> +			 <0x5d00000 0x00 0x5d00000 0x20000>;
> +		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
> +
> +		main_r5fss0_core0: r5f@5c00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5c00000 0x00010000>,
> +			      <0x5c10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <279>;
> +			ti,sci-proc-ids = <0x06 0xff>;
> +			resets = <&k3_reset 279 1>;
> +			firmware-name = "j721s2-main-r5f0_0-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +
> +		main_r5fss0_core1: r5f@5d00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5d00000 0x00010000>,
> +			      <0x5d10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <280>;
> +			ti,sci-proc-ids = <0x07 0xff>;
> +			resets = <&k3_reset 280 1>;
> +			firmware-name = "j721s2-main-r5f0_1-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +	};
> +
> +	main_r5fss1: r5fss@5e00000 {
> +		compatible = "ti,j721s2-r5fss";
> +		ti,cluster-mode = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
> +			 <0x5f00000 0x00 0x5f00000 0x20000>;
> +		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> +
> +		main_r5fss1_core0: r5f@5e00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5e00000 0x00010000>,
> +			      <0x5e10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <281>;
> +			ti,sci-proc-ids = <0x08 0xff>;
> +			resets = <&k3_reset 281 1>;
> +			firmware-name = "j721s2-main-r5f1_0-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +
> +		main_r5fss1_core1: r5f@5f00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5f00000 0x00010000>,
> +			      <0x5f10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <282>;
> +			ti,sci-proc-ids = <0x09 0xff>;
> +			resets = <&k3_reset 282 1>;
> +			firmware-name = "j721s2-main-r5f1_1-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +	};
> +
> +	c71_0: dsp@64800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x64800000 0x00 0x00080000>,
> +		      <0x00 0x64e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <8>;
> +		ti,sci-proc-ids = <0x30 0xff>;
> +		resets = <&k3_reset 8 1>;
> +		firmware-name = "j721s2-c71_0-fw";
> +	};
> +
> +	c71_1: dsp@65800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x65800000 0x00 0x00080000>,
> +		      <0x00 0x65e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <11>;
> +		ti,sci-proc-ids = <0x31 0xff>;
> +		resets = <&k3_reset 11 1>;
> +		firmware-name = "j721s2-c71_1-fw";
> +	};
>  };
> -- 
> 2.34.1
>
Nishanth Menon June 1, 2023, 3 p.m. UTC | #2
On 17:09-20230529, Hari Nagalla wrote:
[...]
> +&mcu_r5fss0_core0 {
> +	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;

I just noticed this, and noticed, this has been going on for quite some
time and was slipped
Use:
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;

and respin. I am in the middle of cleaning up the ones that have crept
in already on too many platforms already.

> +	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
> +			<&mcu_r5fss0_core0_memory_region>;
> +};