From patchwork Tue Mar 21 06:54:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 665695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 784A3C74A5B for ; Tue, 21 Mar 2023 06:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230273AbjCUGzF (ORCPT ); Tue, 21 Mar 2023 02:55:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229923AbjCUGzD (ORCPT ); Tue, 21 Mar 2023 02:55:03 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA2242597C; Mon, 20 Mar 2023 23:55:01 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32L6sn9J047778; Tue, 21 Mar 2023 01:54:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679381689; bh=5CNu2kNv4UF99KFN6mTph9taqDlCm7JW6S2CyHg/1o8=; h=From:To:CC:Subject:Date; b=OCiUKZt+6Q+jcvGZSkcEXZvfybUdTFuw93eRC7TDYjQFQp9UIC+/sGVdvdi/40oVs Lh36VecRqfsglX/Uh1W9GX5gpTuHX2eaB/8/hl5xKz6vJTqath6BzDWI+ustebM/Rc JKJ5JbNqN0Cc3LnFpXl+8bLIM5fa1PSQkS6RzqvE= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32L6snXm119528 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Mar 2023 01:54:49 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Mar 2023 01:54:48 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Mar 2023 01:54:48 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32L6slvN112205; Tue, 21 Mar 2023 01:54:48 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , , Subject: [PATCH v2 0/4] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Date: Tue, 21 Mar 2023 12:24:43 +0530 Message-ID: <20230321065447.6997-1-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series adds device tree nodes for Multi Channel Serial Peripheral Interface (MCSPI) on J721E, J7200, J721S2 and J784S4 platforms. All the MCSPI instances are disabled by default and can be enabled through overlays as required, the changes were tested using spidev loopback test for all instances and the data verified only for main_spi4 which is connected internally as slave to mcu_spi2 for all existing J7 devices. V1->V2: * Address Nishanth's feedback, combine main, mcu domain MCSPI node addition changes to single commit per SoC. Vaishnav Achath (4): arm64: dts: ti: k3-j721e: Add MCSPI nodes arm64: dts: ti: k3-j7200: Add MCSPI nodes arm64: dts: ti: k3-j721s2: Add MCSPI nodes arm64: dts: ti: k3-j784s4: Add MCSPI nodes arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 +++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 33 +++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 33 +++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 33 +++++++ 8 files changed, 484 insertions(+)