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[v3,0/4] MediaTek MT6735 main clock and reset drivers

Message ID 20230225094246.261697-1-y.oudjana@protonmail.com
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Series MediaTek MT6735 main clock and reset drivers | expand

Message

Yassine Oudjana Feb. 25, 2023, 9:42 a.m. UTC 
From: Yassine Oudjana <y.oudjana@protonmail.com>

These patches are part of a larger effort to support the MT6735 SoC family in mainline
Linux. More patches (unsent or sent and pending review or revision) can be found here[1].

This series adds support for the main clock and reset controllers on the
Mediatek MT6735 SoC:
- apmixedsys (global PLLs)
- topckgen (global divisors and muxes)
- infracfg (gates and resets for internal components)
- pericfg (gates and resets for peripherals)

MT6735 has other more specialized clock/reset controllers, support for which is
not included in this series:
- mfgcfg (GPU)
- imgsys (camera)
- mmsys (display)
- vdecsys (video decoder)
- vencsys (video encoder)
- audsys (audio)

Changes since v2:
- Add "CLK_" prefix to infracfg and pericfg clock definitions to avoid possible
  clashes with reset bindings.
- Replace "_RST" suffix with "RST_" prefix to maintain consistency with clock bindings.
- Use macros to define clocks.
- Abandon mtk_clk_simple_probe/mtk_clk_simple_remove in favor of custom functions in apmixedsys
  and topckgen drivers for the time being. 
- Capitalize T in MediaTek in MODULE_DESCRIPTION.
Changes since v1:
- Rebase on some pending patches.
- Move common clock improvements to a separate series.
- Use mtk_clk_simple_probe/remove after making them support several clock types
  in said series.
- Combine all 4 drivers into one patch, and use one Kconfig symbol for all
  following a conversation seen on a different series[2].
- Correct APLL2 registers in apmixedsys driver (were offset backwards by 0x4).
- Make irtx clock name lower case to match the other clocks.

[1] https://gitlab.com/mt6735-mainline/linux/-/commits/mt6735-staging
[2] https://lore.kernel.org/linux-mediatek/CAGXv+5H4gF5GXzfk8mjkG4Kry8uCs1CQbKoViBuc9LC+XdHH=A@mail.gmail.com/

Yassine Oudjana (4):
  dt-bindings: clock: Add MediaTek MT6735 clock bindings
  dt-bindings: reset: Add MediaTek MT6735 reset bindings
  dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles
  clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset
    drivers

 .../arm/mediatek/mediatek,infracfg.yaml       |   8 +-
 .../arm/mediatek/mediatek,pericfg.yaml        |   1 +
 .../bindings/clock/mediatek,apmixedsys.yaml   |   4 +-
 .../bindings/clock/mediatek,topckgen.yaml     |   4 +-
 MAINTAINERS                                   |  16 +
 drivers/clk/mediatek/Kconfig                  |   9 +
 drivers/clk/mediatek/Makefile                 |   1 +
 drivers/clk/mediatek/clk-mt6735-apmixedsys.c  | 139 ++++++
 drivers/clk/mediatek/clk-mt6735-infracfg.c    |  78 +++
 drivers/clk/mediatek/clk-mt6735-pericfg.c     |  91 ++++
 drivers/clk/mediatek/clk-mt6735-topckgen.c    | 450 ++++++++++++++++++
 .../clock/mediatek,mt6735-apmixedsys.h        |  16 +
 .../clock/mediatek,mt6735-infracfg.h          |  25 +
 .../clock/mediatek,mt6735-pericfg.h           |  37 ++
 .../clock/mediatek,mt6735-topckgen.h          |  79 +++
 .../reset/mediatek,mt6735-infracfg.h          |  31 ++
 .../reset/mediatek,mt6735-pericfg.h           |  31 ++
 17 files changed, 1015 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
 create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h

Comments

Krzysztof Kozlowski Feb. 27, 2023, 8:18 a.m. UTC | #1 
On 25/02/2023 10:42, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
> 
> Add clock definitions for the main clock controllers of MT6735 (apmixedsys,
> topckgen, infracfg and pericfg).
> 
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  MAINTAINERS                                   | 10 +++
>  .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>  .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>  .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>  .../clock/mediatek,mt6735-topckgen.h          | 79 +++++++++++++++++++
>  5 files changed, 167 insertions(+)

You should squash it with other part of binding. What is the reason
behind splitting one binding into three patches?

Best regards,
Krzysztof
Yassine Oudjana Feb. 27, 2023, 8:29 a.m. UTC | #2 
On Mon, Feb 27 2023 at 09:18:45 AM +01:00:00, Krzysztof Kozlowski 
<krzysztof.kozlowski@linaro.org> wrote:
> On 25/02/2023 10:42, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Add clock definitions for the main clock controllers of MT6735 
>> (apmixedsys,
>>  topckgen, infracfg and pericfg).
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  Acked-by: Rob Herring <robh@kernel.org>
>>  ---
>>   MAINTAINERS                                   | 10 +++
>>   .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>>   .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>>   .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>>   .../clock/mediatek,mt6735-topckgen.h          | 79 
>> +++++++++++++++++++
>>   5 files changed, 167 insertions(+)
> 
> You should squash it with other part of binding. What is the reason
> behind splitting one binding into three patches?

It seemed logical to me that each of clock and reset bindings as well 
as documentation would be separate parts especially since they go in 
different paths, but if combining them is how it's done then sure, I'll 
squash them and resend.
Krzysztof Kozlowski Feb. 27, 2023, 9:08 a.m. UTC | #3 
On 27/02/2023 09:29, Yassine Oudjana wrote:
> 
> On Mon, Feb 27 2023 at 09:18:45 AM +01:00:00, Krzysztof Kozlowski 
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 25/02/2023 10:42, Yassine Oudjana wrote:
>>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>>>
>>>  Add clock definitions for the main clock controllers of MT6735 
>>> (apmixedsys,
>>>  topckgen, infracfg and pericfg).
>>>
>>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>>  Acked-by: Rob Herring <robh@kernel.org>
>>>  ---
>>>   MAINTAINERS                                   | 10 +++
>>>   .../clock/mediatek,mt6735-apmixedsys.h        | 16 ++++
>>>   .../clock/mediatek,mt6735-infracfg.h          | 25 ++++++
>>>   .../clock/mediatek,mt6735-pericfg.h           | 37 +++++++++
>>>   .../clock/mediatek,mt6735-topckgen.h          | 79 
>>> +++++++++++++++++++
>>>   5 files changed, 167 insertions(+)
>>
>> You should squash it with other part of binding. What is the reason
>> behind splitting one binding into three patches?
> 
> It seemed logical to me that each of clock and reset bindings as well 
> as documentation would be separate parts especially since they go in 

I don't understand. All of these are bindings. What do you mean by
"documentation"?

> different paths, but if combining them is how it's done then sure, I'll 
> squash them and resend.

They cannot go different paths and your submissions creates false
impression they can. If you want to see - apply these on separate
branches and test if: driver compiles and paths to files in doc are not
broken. Answer: driver won't compile and paths will point to
non-existing files.


Best regards,
Krzysztof