From patchwork Fri Feb 24 10:58:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E912DC61DA3 for ; Fri, 24 Feb 2023 11:00:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbjBXLAJ (ORCPT ); Fri, 24 Feb 2023 06:00:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229980AbjBXK7k (ORCPT ); Fri, 24 Feb 2023 05:59:40 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C23863DD3 for ; Fri, 24 Feb 2023 02:59:16 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id ko13so16989340plb.13 for ; Fri, 24 Feb 2023 02:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=4nUiMlzdFVdylVAwvGF2mzTH+MQ8jxdhSSAuOwiDOrk=; b=sD8fpV1iBm1gOL4hX7ssWFPYQXWuJgQM8zfQlrHHNH7z4u/zl+ABhh3jZ9pqJ1wVj0 B2vre9cVycIC8F/bA4JpHy3L9p4kxWrr1DAGUo7LNSZeIlOGA68QahK65J/W34IjD4aW txEgU8+p3DQaH/gFVaGvmVbba0SofD0L49Z23g3ywpEmWZsyv99YcS/9RAAx3P+/BAYa J/Nxq3++RIozCHDwOm+WIHfuEA/Ji7ud0cjY/xYFjubCxZLu9QA2Lka1F4jxN5LMG7iN ZMFlit9zuVRtpx0vpb19qfbkT/3YkzQLseDNNBRnD7eNE1tIH/lS1VoNnOoHCkiCweTA hV+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4nUiMlzdFVdylVAwvGF2mzTH+MQ8jxdhSSAuOwiDOrk=; b=kOmWI2c1WAYOyZuhar1PY5TmqqDy9ILvxOJWKc7H7C05Op9AOjJDxVP2k0PIYPqY8Y B9YRUY/dYFmsFpUfSMWKE4/WAmhJPVdN2B8gKUcCC/ikauqzLf7MaudvlH/F7LIsQaEI h03G977tI2RmRQIZwMIPU++BvqKJ+NIY8gmzDQ3KsB5e1bbiLoEy44GbODi4Juj5M/6n X5VwxAVKcEqt8KZEEeCS6CyMzND3q1Ghwvkg88gZuEadIVQ3b70V3sPnO75BWT4kuGMi SIQFhSH8JTNa9eLN2j0w2bvnhpZcDg3URV1LGQnCfg/qphxUBaCfAQRTAd7RasR/UrD7 yeKg== X-Gm-Message-State: AO0yUKU+BhNec6q5pscSXqWE/JD2Sx+oyi2NSUwYoteM4nYbOJQ7AK3b S0Ckftvfu3bvdOoXkcCkeot6 X-Google-Smtp-Source: AK7set/S+ZygCYuCUKF9LEBR1rJYfsKfJShN1QO28O1CvLDthNfwy1uzHl2p2i6zudrTi6g/rOYYrw== X-Received: by 2002:a17:90b:388f:b0:234:6b7e:d016 with SMTP id mu15-20020a17090b388f00b002346b7ed016mr15132219pjb.22.1677236355675; Fri, 24 Feb 2023 02:59:15 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:15 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 00/13] Add PCIe RC support to Qcom SDX55 SoC Date: Fri, 24 Feb 2023 16:28:53 +0530 Message-Id: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, This series adds PCIe RC support to the Qcom SDX55 SoC. The PCIe controller in SDX55 can act as both Root Complex and Endpoint but only one mode at a time i.e., the mode cannot be switched during runtime. This series has been tested on Thundercomm T55 board having QCA6390 WLAN chipset connected to the PCIe controller. For powering up the WLAN chipset, an out-of-tree patch has been used since we do not have a proper driver in mainline to handle the power supplies. NOTE: Even with this series, I couldn't get network connectivity using QCA6390. But that's due to ath11k regression for which I've filed a bug report: https://bugzilla.kernel.org/show_bug.cgi?id=217070 Merging strategy ---------------- PCI and binding patches through PCI tree PHY patches through PHY tree Devicetree patches through Qcom tree Thanks, Mani Changes in v2: * Added patche to move status property down * Added patch to list property values vertically * Addressed comments from Konrad * Collected review tags * Fixed review tag for dts patch Manivannan Sadhasivam (13): dt-bindings: PCI: qcom: Update maintainers entry dt-bindings: PCI: qcom: Add iommu properties dt-bindings: PCI: qcom: Add SDX55 SoC dt-bindings: PCI: qcom-ep: Fix the unit address used in example ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} ARM: dts: qcom: sdx55: Add support for PCIe RC controller ARM: dts: qcom: sdx55: List the property values vertically ARM: dts: qcom: sdx55-t55: Enable PCIe RC support ARM: dts: qcom: sdx55-t55: Move "status" property down phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 phy: qcom-qmp-pcie: Add RC init sequence for SDX55 PCI: qcom: Add support for SDX55 SoC .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/qcom,pcie.yaml | 35 +++- arch/arm/boot/dts/qcom-sdx55-t55.dts | 53 +++++- .../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 179 ++++++++++++++---- drivers/pci/controller/dwc/pcie-qcom.c | 4 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 91 +++++++-- .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 + 8 files changed, 303 insertions(+), 65 deletions(-)