[v5,0/7] clk: qcom: msm8996: add APCS clock driver

The sys_apcs_aux clock can be used by CPU and CBF clock drivers to drive
those clocks from GPLL0 while doing initial setup. Add simple driver to
setup and export this clock.

Changes since v4:
- Expand comments in the apcs-msm8996 driver describing the delay and
  the reason for setting up the sys_apcs_aux clock as a fixed rate
  rather than a fixed factor clock.

Changes since v3:
- Split the patch 3/6 into two: first one moves existing strings, second
  one adds new compatible strings to the conditionals.

Changes since v2:
- Added the conditional clause to schema forbidding usage of clocks and
  clock-names on platforms which do not pass additional clocks to the
  APCS device node (Krzysztof)
- Added SDX55 compat string
- Moved MSM8976 compat to the list of platforms using syscon.

Changes since v1:
- Removed the clk.h header inclusion (Stephen)
- Changed the module license from GPL v2 to bare GPL.


Dmitry Baryshkov (7):
  dt-bindings: mailbox: qcom: add SDX55 compatible
  dt-bindings: mailbox: qcom: enable syscon compatible for msm8976
  dt-bindings: mailbox: qcom: correct the list of platforms using clocks
  dt-bindings: mailbox: qcom: add missing platforms to conditional
    clauses
  dt-bindings: mailbox: qcom: add #clock-cells to msm8996 example
  mailbox: qcom-apcs-ipc: enable APCS clock device for MSM8996
  clk: qcom: add the driver for the MSM8996 APCS clocks

 .../mailbox/qcom,apcs-kpss-global.yaml        | 37 ++++++--
 drivers/clk/qcom/Makefile                     |  2 +-
 drivers/clk/qcom/apcs-msm8996.c               | 88 +++++++++++++++++++
 drivers/mailbox/qcom-apcs-ipc-mailbox.c       |  2 +-
 4 files changed, 118 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/qcom/apcs-msm8996.c

On 27.01.2023 00:03, Dmitry Baryshkov wrote:
> Add a simple driver handling the APCS clocks on MSM8996. For now it
> supports just a single aux clock, linking GPLL0 to CPU and CBF clocks.
> 
> Note, there is little sense in registering sys_apcs_aux as a child of
> gpll0. The PLL is always-on. And listing the gpll0 as a property of the
> apcs would delay its probing until the GCC has been probed (while we
> would like for the apcs to be probed as early as possible).
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/Makefile       |  2 +-
>  drivers/clk/qcom/apcs-msm8996.c | 88 +++++++++++++++++++++++++++++++++
>  2 files changed, 89 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/qcom/apcs-msm8996.c
> 
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 3194465dd02c..a8ed1f38b2f7 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -52,7 +52,7 @@ obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o
>  obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
>  obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o
>  obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
> -obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
> +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += apcs-msm8996.o clk-cpu-8996.o
>  obj-$(CONFIG_QCOM_CLK_APCS_SDX55) += apcs-sdx55.o
>  obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
>  obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
> diff --git a/drivers/clk/qcom/apcs-msm8996.c b/drivers/clk/qcom/apcs-msm8996.c
> new file mode 100644
> index 000000000000..48d22572b6ae
> --- /dev/null
> +++ b/drivers/clk/qcom/apcs-msm8996.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Qualcomm APCS clock controller driver
> + *
> + * Copyright (c) 2022, Linaro Limited
> + * Author: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#define APCS_AUX_OFFSET	0x50
> +
> +#define APCS_AUX_DIV_MASK GENMASK(17, 16)
> +#define APCS_AUX_DIV_2 0x1
> +
> +static int qcom_apcs_msm8996_clk_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device *parent = dev->parent;
> +	struct regmap *regmap;
> +	struct clk_hw *hw;
> +	unsigned int val;
> +	int ret = -ENODEV;
> +
> +	regmap = dev_get_regmap(parent, NULL);
> +	if (!regmap) {
> +		dev_err(dev, "failed to get regmap: %d\n", ret);
> +		return ret;
> +	}
> +
> +	regmap_read(regmap, APCS_AUX_OFFSET, &val);
> +	regmap_update_bits(regmap, APCS_AUX_OFFSET, APCS_AUX_DIV_MASK,
> +			   FIELD_PREP(APCS_AUX_DIV_MASK, APCS_AUX_DIV_2));
> +
> +	/*
> +	 * This clock is used during CPU cluster setup while setting up CPU PLLs.
> +	 * Add hardware mandated delay to make sure that the sys_apcs_aux clock
> +	 * is stable (after setting the divider) before continuing
> +	 * bootstrapping to keep CPUs from ending up in a weird state.
> +	 */
> +	udelay(5);
> +
> +	/*
> +	 * As this clocks is a parent of the CPU cluster clocks and is actually
> +	 * used as a parent during CPU clocks setup, we want for it to gegister
> +	 * as early as possible, without letting fw_devlink to delay probing of
> +	 * either of the drivers.
> +	 *
> +	 * The sys_apcs_aux is a child (divider) of gpll0, but we register it
> +	 * as a fixed rate clock instead to ease bootstrapping procedure. By
> +	 * doing this we make sure that CPU cluster clocks are able to be setup
> +	 * early during the boot process (as it is recommended by Qualcomm).
> +	 */
> +	hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
> +}
> +
> +static struct platform_driver qcom_apcs_msm8996_clk_driver = {
> +	.probe = qcom_apcs_msm8996_clk_probe,
> +	.driver = {
> +		.name = "qcom-apcs-msm8996-clk",
> +	},
> +};
> +
> +/* Register early enough to fix the clock to be used for other cores */
> +static int __init qcom_apcs_msm8996_clk_init(void)
> +{
> +	return platform_driver_register(&qcom_apcs_msm8996_clk_driver);
> +}
> +postcore_initcall(qcom_apcs_msm8996_clk_init);
> +
> +static void __exit qcom_apcs_msm8996_clk_exit(void)
> +{
> +	platform_driver_unregister(&qcom_apcs_msm8996_clk_driver);
> +}
> +module_exit(qcom_apcs_msm8996_clk_exit);
> +
> +MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Qualcomm MSM8996 APCS clock driver");

On 27/01/2023 01:03, Dmitry Baryshkov wrote:
> The sys_apcs_aux clock can be used by CPU and CBF clock drivers to drive
> those clocks from GPLL0 while doing initial setup. Add simple driver to
> setup and export this clock.

Jassi, please excuse me for this ping. Since the only questions are 
related to the clock driver (and hopefully they all are resolved), do 
you plan to merge the patches 1-6 for 6.3?

> 
> Changes since v4:
> - Expand comments in the apcs-msm8996 driver describing the delay and
>    the reason for setting up the sys_apcs_aux clock as a fixed rate
>    rather than a fixed factor clock.
> 
> Changes since v3:
> - Split the patch 3/6 into two: first one moves existing strings, second
>    one adds new compatible strings to the conditionals.
> 
> Changes since v2:
> - Added the conditional clause to schema forbidding usage of clocks and
>    clock-names on platforms which do not pass additional clocks to the
>    APCS device node (Krzysztof)
> - Added SDX55 compat string
> - Moved MSM8976 compat to the list of platforms using syscon.
> 
> Changes since v1:
> - Removed the clk.h header inclusion (Stephen)
> - Changed the module license from GPL v2 to bare GPL.
> 
> 
> Dmitry Baryshkov (7):
>    dt-bindings: mailbox: qcom: add SDX55 compatible
>    dt-bindings: mailbox: qcom: enable syscon compatible for msm8976
>    dt-bindings: mailbox: qcom: correct the list of platforms using clocks
>    dt-bindings: mailbox: qcom: add missing platforms to conditional
>      clauses
>    dt-bindings: mailbox: qcom: add #clock-cells to msm8996 example
>    mailbox: qcom-apcs-ipc: enable APCS clock device for MSM8996
>    clk: qcom: add the driver for the MSM8996 APCS clocks
> 
>   .../mailbox/qcom,apcs-kpss-global.yaml        | 37 ++++++--
>   drivers/clk/qcom/Makefile                     |  2 +-
>   drivers/clk/qcom/apcs-msm8996.c               | 88 +++++++++++++++++++
>   drivers/mailbox/qcom-apcs-ipc-mailbox.c       |  2 +-
>   4 files changed, 118 insertions(+), 11 deletions(-)
>   create mode 100644 drivers/clk/qcom/apcs-msm8996.c
>

Quoting Dmitry Baryshkov (2023-01-26 15:03:19)
> diff --git a/drivers/clk/qcom/apcs-msm8996.c b/drivers/clk/qcom/apcs-msm8996.c
> new file mode 100644
> index 000000000000..48d22572b6ae
> --- /dev/null
> +++ b/drivers/clk/qcom/apcs-msm8996.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Qualcomm APCS clock controller driver
> + *
[...]
> +
> +       /*
> +        * This clock is used during CPU cluster setup while setting up CPU PLLs.
> +        * Add hardware mandated delay to make sure that the sys_apcs_aux clock
> +        * is stable (after setting the divider) before continuing
> +        * bootstrapping to keep CPUs from ending up in a weird state.
> +        */
> +       udelay(5);
> +
> +       /*
> +        * As this clocks is a parent of the CPU cluster clocks and is actually
> +        * used as a parent during CPU clocks setup, we want for it to gegister

s/gegister/register/

> +        * as early as possible, without letting fw_devlink to delay probing of
> +        * either of the drivers.

Ok, good to know fw_devlink is the problem in this case.

> +        *
> +        * The sys_apcs_aux is a child (divider) of gpll0, but we register it
> +        * as a fixed rate clock instead to ease bootstrapping procedure. By
> +        * doing this we make sure that CPU cluster clocks are able to be setup
> +        * early during the boot process (as it is recommended by Qualcomm).
> +        */
> +       hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000);
> +       if (IS_ERR(hw))
> +               return PTR_ERR(hw);
> +