From patchwork Tue Jan 24 12:47:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 646162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 712FBC25B4E for ; Tue, 24 Jan 2023 12:47:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233973AbjAXMrY (ORCPT ); Tue, 24 Jan 2023 07:47:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233952AbjAXMrX (ORCPT ); Tue, 24 Jan 2023 07:47:23 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75FC13E622 for ; Tue, 24 Jan 2023 04:47:22 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id bk16so13741843wrb.11 for ; Tue, 24 Jan 2023 04:47:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NQY35x77x8kOxBsXweZuI8QRw64wWTJF3dft8bDEqWY=; b=PiMMyODDWRQalMesG3gfe5bcjonEYBSCvJw/RQKhDkj8rVDL85SL3V7NUqvU9Tx7mg /jjHHUivYBes8xRQhqokxAILXlynP0KUbQEtTYVND0yahLoiHyL3CLqktoQr+Y/NopUX mHRTyBITWCcndRFO3zkI2UKFAEi1CwWBHFsWy6+Opp7h9M8nLoXOeuuh6BEqXcKbE3p0 NNN3ugOyaK/TpA53cLo0F9droSpVeNMnGo0xnmk7yd7LjVYiVMfYC550vflqOhnLpUm8 P0m4j9boYN5yD3rSOCy0pwlVHipMjULnvDxnMtDMUqcFUmY88DJwyEw9lZLbaGbf59Hn 8EHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NQY35x77x8kOxBsXweZuI8QRw64wWTJF3dft8bDEqWY=; b=6zpYk5Dfqtt59oFbjxDbuiYedwJDRwAqDZAUoUR4y1oNuKrKo+7BT9JXNsSl0LrlqG KPB2G7QL1LFxTwa9429vdI0sLyDJMV85E0p59y9dKR6Y4oEEG77tqSEDZlno6DvkWm4R KB2u9mp0SxWfLa22f1zbmLT47bz8AZq0HV4JnVwOkN1iIcyTdCsquZ2Joy8OpjW8HEhH XI9Y4HV5GpayeglnAZXDl34A6QgO4eSoKQr7gOMXkmLhe0ylopJKAI3PZDJtT8PlTiYt NBzDHzK7sBpZ7PkxokLGkE5G+KGNmBEQQEneb5KBpRDdH4Rdpi289q+mySvVQ0dvHNK/ /j2g== X-Gm-Message-State: AFqh2kp2EZ/Ksee4AjbZtErO+YY1Qdql8Qjkdk1nd6lfvjMMRaA7Bxbu Oss5efXsDxW0NxbghsEq0gBbOg== X-Google-Smtp-Source: AMrXdXv5jJuf7e8t1rbwRrcG+mysui5oKWwSENlk39CSpsFbmdFPiRUPasU4MUTSIxXuNY1nRxqWrg== X-Received: by 2002:a5d:457a:0:b0:2bb:e993:6c85 with SMTP id a26-20020a5d457a000000b002bbe9936c85mr23682176wrc.35.1674564440879; Tue, 24 Jan 2023 04:47:20 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id a5-20020a5d5705000000b002bdbde1d3absm1766840wrv.78.2023.01.24.04.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 04:47:20 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Date: Tue, 24 Jan 2023 14:47:02 +0200 Message-Id: <20230124124714.3087948-1-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For changelogs please look at each patch individually. Abel Vesa (12): dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 phy: qcom-qmp: pcs: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add SM8550 PCIe support arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 30 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 37 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 203 +++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 25 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 369 +++++++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 + .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++ .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 6 + 13 files changed, 846 insertions(+), 17 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h