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[v2,0/3] Add a devicetree for the Aldec PolarFire SoC TySoM

Message ID 20230111124106.2417152-1-conor.dooley@microchip.com
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Series Add a devicetree for the Aldec PolarFire SoC TySoM | expand

Message

Conor Dooley Jan. 11, 2023, 12:41 p.m. UTC 
Hey All,

The board has 32 GB of DDR but the DT I have access to only has a small
bit of that mapped. I tried accessing more DDR, but it was not possible
with the FPGA design as things stand. I'd rather have the devicetree
match what the vendor is shipping, so left the design/DDR as-was.

Other than fixing some minor bits from Krzysztof, the other change is
that I dropped the PCI node as that doesn't appear to be mapped.

Thanks,
Conor.

v1: https://lore.kernel.org/linux-riscv/20220906121525.3212705-1-conor.dooley@microchip.com/

Conor Dooley (3):
  dt-bindings: vendor-prefixes: Add entry for Aldec
  dt-bindings: riscv: microchip: document the Aldec TySoM
  riscv: dts: microchip: add the Aldec TySoM's devicetree

 .../devicetree/bindings/riscv/microchip.yaml  |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/riscv/boot/dts/microchip/Makefile        |   1 +
 .../dts/microchip/mpfs-tysom-m-fabric.dtsi    |  47 +++++
 .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 ++++++++++++++++++
 5 files changed, 216 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts