| Message ID | 20230110121316.24892-1-quic_devipriy@quicinc.com |
|---|---|
| Headers | show |
| Series | Add minimal boot support for IPQ9574 | expand |
On 1/11/2023 3:16 PM, Krzysztof Kozlowski wrote: > On 10/01/2023 13:13, devi priya wrote: >> Add pinctrl definitions for the TLMM of IPQ9574 >> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: devi priya <quic_devipriy@quicinc.com> >> --- >> drivers/pinctrl/qcom/Kconfig | 10 + >> drivers/pinctrl/qcom/Makefile | 1 + >> drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++ >> 3 files changed, 1014 insertions(+) >> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c >> >> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig >> index 1378ddca084f..a9b4b07e3de0 100644 >> --- a/drivers/pinctrl/qcom/Kconfig >> +++ b/drivers/pinctrl/qcom/Kconfig >> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018 >> Qualcomm Technologies Inc. IPQ6018 platform. Select this for >> IPQ6018. >> >> +config PINCTRL_IPQ9574 >> + tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver" >> + depends on GPIOLIB && OF > > Look at other entries and use similar style. Sure, will do! > > Best regards, > Krzysztof > Best Regards, Devi Priya
On 1/11/2023 8:33 PM, Krzysztof Kozlowski wrote: > On 11/01/2023 15:48, Kathiravan Thirumoorthy wrote: >> >> On 1/10/2023 5:43 PM, devi priya wrote: >>> Enables clk & pinctrl related configs >>> >>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >>> Signed-off-by: devi priya <quic_devipriy@quicinc.com> >>> --- >>> arch/arm64/configs/defconfig | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >>> index 851e8f9be06d..e0ae0996d5ad 100644 >>> --- a/arch/arm64/configs/defconfig >>> +++ b/arch/arm64/configs/defconfig >>> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y >>> CONFIG_PINCTRL_MSM=y >>> CONFIG_PINCTRL_IPQ8074=y >>> CONFIG_PINCTRL_IPQ6018=y >>> +CONFIG_PINCTRL_IPQ9574=y >> Please move this after IPQ8074, to keep it in ascending order. We can >> move the IPQ6018 config before IPQ8074. > > This must match savedefconfig order, not alphabetical. Understood! > > Best regards, > Krzysztof > Best Regards, Devi Priya
On 13/01/2023 14:24, Devi Priya wrote: >>> + properties: >>> + pins: >>> + description: >>> + List of gpio pins affected by the properties specified in this >>> + subnode. >>> + items: >>> + oneOf: >>> + - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$" >>> + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, >>> + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, >>> + qdsd_data3 ] >> >> These are ordered by name. > The enum values seem to be ordered alphabetically. > could you please help us understand the ordering? q goes before s >> >>> + minItems: 1 >>> + maxItems: 8 >>> + Best regards, Krzysztof
On 1/13/2023 7:46 PM, Krzysztof Kozlowski wrote: > On 13/01/2023 14:24, Devi Priya wrote: >>>> + properties: >>>> + pins: >>>> + description: >>>> + List of gpio pins affected by the properties specified in this >>>> + subnode. >>>> + items: >>>> + oneOf: >>>> + - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$" >>>> + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, >>>> + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, >>>> + qdsd_data3 ] >>> >>> These are ordered by name. >> The enum values seem to be ordered alphabetically. >> could you please help us understand the ordering? > > q goes before s Oops! sorry. Will update > >>> >>>> + minItems: 1 >>>> + maxItems: 8 >>>> + > > Best regards, > Krzysztof > Best Regards, Devi Priya
The IPQ9574 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq9574-al02-c7 board POOVENDHAN SELVARAJ (1): arm64: dts: Add ipq9574 SoC and AL02 board support devi priya (6): dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings pinctrl: qcom: Add IPQ9574 pinctrl driver dt-bindings: qcom: Add ipq9574 bindings arm64: defconfig: Enable IPQ9574 SoC base configs .../devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,gcc-other.yaml | 4 + .../devicetree/bindings/clock/qcom,gcc.yaml | 9 +- .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 129 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 69 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 318 ++ arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9574.c | 4706 +++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++ include/dt-bindings/clock/qcom,gcc-ipq9574.h | 226 + include/dt-bindings/reset/qcom,gcc-ipq9574.h | 164 + 16 files changed, 6657 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq9574.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h base-commit: 1fe4fd6f5cad346e598593af36caeadc4f5d4fa9