mbox series

[0/8] soc: mediatek: MT8365 power support

Message ID 20230105170735.1637416-1-msp@baylibre.com
Headers show
Series soc: mediatek: MT8365 power support | expand

Message

Markus Schneider-Pargmann Jan. 5, 2023, 5:07 p.m. UTC 
Hi,

sorry for the long delay, here is an update to the mt8365 power domain
series. Thanks for all your feedback, I hope I addressed everything. As
Matthias brought up some good points, I got back to try to make the
WAY_EN feature a bit more understandable with less code duplication. I
added a few patches to prepare the driver for the WAY_EN patch. I hope
it is better to understand now.

Thank you!

Best,
Markus

Changes in v4:
- Redesigned WAY_EN patch and split it up in smaller patches.
- Added two documentation patches.
- Added mediatek,infracfg-nao field to the binding.

Changes in v3:
- Mainly redesigned WAY_EN patch to be easier to understand
- Rebased onto v6.0-rc1
- Several other stuff that is described in the individual patches

Changes in v2:
- Updated error handling path for scpsys_power_on()
- Minor updates described in each patch

Previous versions:
v1 - https://lore.kernel.org/linux-mediatek/20220530204214.913251-1-fparent@baylibre.com/
v2 - https://lore.kernel.org/linux-mediatek/20220725081853.1636444-1-msp@baylibre.com/
v3 - https://lore.kernel.org/linux-mediatek/20220822144303.3438467-1-msp@baylibre.com/

Alexandre Bailon (2):
  soc: mediatek: Add support for WAY_EN operations
  soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap

Fabien Parent (2):
  dt-bindings: power: Add MT8365 power domains
  soc: mediatek: pm-domains: Add support for MT8365

Markus Schneider-Pargmann (4):
  soc: mediatek: pm-domains: Split bus_prot_mask
  soc: mediatek: pm-domains: Create bus protection operation functions
  soc: mediatek: pm-domains: Document scpsys_bus_prot_data
  soc: mediatek: pm-domains: Fix caps field documentation

 .../power/mediatek,power-controller.yaml      |   6 +
 drivers/soc/mediatek/mt8365-pm-domains.h      | 147 ++++++++++++++++++
 drivers/soc/mediatek/mtk-pm-domains.c         | 135 +++++++++++-----
 drivers/soc/mediatek/mtk-pm-domains.h         |  37 ++++-
 .../dt-bindings/power/mediatek,mt8365-power.h |  19 +++
 5 files changed, 302 insertions(+), 42 deletions(-)
 create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
 create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h

Comments

Rob Herring Jan. 8, 2023, 10:07 p.m. UTC | #1 
On Thu, 05 Jan 2023 18:07:28 +0100, Markus Schneider-Pargmann wrote:
> From: Fabien Parent <fparent@baylibre.com>
> 
> Add power domains dt-bindings for MT8365.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> ---
> 
> Notes:
>     Changes in v4:
>     - Add infracfg_nao as it is used by mt8365
> 
>     Changes in v3:
>     - Renamed mt8365-power.h to mediatek,mt8365-power.h
> 
>     Changes in v2:
>     - Made include/dt-bindings/power/mt8365-power.h dual-license.
> 
>  .../power/mediatek,power-controller.yaml      |  6 ++++++
>  .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++
>  2 files changed, 25 insertions(+)
>  create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Markus Schneider-Pargmann Feb. 20, 2023, 8:10 p.m. UTC | #2 
Hi Matthias,

On Fri, Feb 03, 2023 at 01:31:58PM +0100, Matthias Brugger wrote:
> 
> 
> On 05/01/2023 18:07, Markus Schneider-Pargmann wrote:
> > From: Fabien Parent <fparent@baylibre.com>
> > 
> > Add power domains dt-bindings for MT8365.
> > 
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > ---
> > 
> > Notes:
> >      Changes in v4:
> >      - Add infracfg_nao as it is used by mt8365
> >      Changes in v3:
> >      - Renamed mt8365-power.h to mediatek,mt8365-power.h
> >      Changes in v2:
> >      - Made include/dt-bindings/power/mt8365-power.h dual-license.
> > 
> >   .../power/mediatek,power-controller.yaml      |  6 ++++++
> >   .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++
> >   2 files changed, 25 insertions(+)
> >   create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h
> > 
> > diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> > index 605ec7ab5f63..a496c43cfa16 100644
> > --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> > @@ -30,6 +30,7 @@ properties:
> >         - mediatek,mt8186-power-controller
> >         - mediatek,mt8192-power-controller
> >         - mediatek,mt8195-power-controller
> > +      - mediatek,mt8365-power-controller
> >     '#power-domain-cells':
> >       const: 1
> > @@ -86,6 +87,7 @@ $defs:
> >                 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
> >                 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
> >                 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
> > +              "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
> >           maxItems: 1
> >         clocks:
> > @@ -113,6 +115,10 @@ $defs:
> >           $ref: /schemas/types.yaml#/definitions/phandle
> >           description: phandle to the device containing the INFRACFG register range.
> > +      mediatek,infracfg-nao:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to the device containing the INFRACFG-NAO register range.
> > +
> 
> 
> Hm, so we have mediatek,mt8365-infracfg defined in mt8365-sys-clock. Also
> the description talks about infracfg_ao. You now introduce INFRACFG-NAO. Is
> that just another system clock block, or is this covered with the
> mediatek,mt8365-infracfg binding?
> 
> We would need to clean that up.

Looking through the datasheet I don't see any clock related registers
for infracfg-nao. So I don't think it is another system clock block. It
seems to be a lot of status registers and debug registers, but not all
of them. It really doesn't seem to have a specific topic here. So from
my point of view it is just a syscon block. Should I add a
mediatek,mt8365-infracfg-nao compatible to the syscon binding
documentation?

Thanks,
Markus

> 
> Regards,
> Matthias
> 
> >         mediatek,smi:
> >           $ref: /schemas/types.yaml#/definitions/phandle
> >           description: phandle to the device containing the SMI register range.
> > diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h
> > new file mode 100644
> > index 000000000000..e6cfd0ec7871
> > --- /dev/null
> > +++ b/include/dt-bindings/power/mediatek,mt8365-power.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
> > +#define _DT_BINDINGS_POWER_MT8365_POWER_H
> > +
> > +#define MT8365_POWER_DOMAIN_MM		0
> > +#define MT8365_POWER_DOMAIN_CONN	1
> > +#define MT8365_POWER_DOMAIN_MFG		2
> > +#define MT8365_POWER_DOMAIN_AUDIO	3
> > +#define MT8365_POWER_DOMAIN_CAM		4
> > +#define MT8365_POWER_DOMAIN_DSP		5
> > +#define MT8365_POWER_DOMAIN_VDEC	6
> > +#define MT8365_POWER_DOMAIN_VENC	7
> > +#define MT8365_POWER_DOMAIN_APU		8
> > +
> > +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */