From patchwork Mon Dec 26 03:10:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88F60C4167B for ; Mon, 26 Dec 2022 03:11:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231516AbiLZDLI (ORCPT ); Sun, 25 Dec 2022 22:11:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231487AbiLZDLG (ORCPT ); Sun, 25 Dec 2022 22:11:06 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB2FDFD4 for ; Sun, 25 Dec 2022 19:11:01 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id f34so14544975lfv.10 for ; Sun, 25 Dec 2022 19:11:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=xCxzLVf2hWUuKQW8OMy2XQ3RUyeAaq22gTKfh7WKh4U=; b=hQIuSbsfbmlPARYuxNQwe4qSwEgYlbiOx6KYQRcH1k0LpsQxmW+FA/gXHE3lcX1p9+ AKL4BAdnuGZ2VsyqMJlruS4ITeqCC4R5hw3Kt5iSLeAuDHfSvNaru1aXeFba9onDONtm U9UusTUy5MT+QGi8a/Zc+2v0n1JhTVNQkyqucWSOsu62dtsRIN2GC1W5DeLp7ssVnDeE fi0HIzu86On5zb+1Xk025AiXdDAdmEXvUgKFK1hCsbQOcGSh2qX8HnpC/CnPdZTgdZZB MTWZ4BLmSeDcNaoPnkkvC1OTY66x9mTOvvo8hBFAB1xDrwJ4vyStdv1CPWrEYOI52bMR NoTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=xCxzLVf2hWUuKQW8OMy2XQ3RUyeAaq22gTKfh7WKh4U=; b=FlJQZxBecb8RAE+r0qSo6akp16JRLKR03zY+dzLOCr4a9FAByDEx6nxLBmIKqT1tNp Hz0GmquqaHlLJIqrOqybqAjgbYcqER/fObRoHE1m3CsVHQO2EdLWOVXsJy766ktKcRBe ooOVVtReTN+pFI7btgC9lg+APxeF5FznW3JE5ALOQPSs/3qjHrV2P1qE2NpH9Uy4ppBo KsXM+io66MShqQ3fZ3/8kgkWKKN36XR/2j0xe8Qmf6pfNO/qaowaDrOdA6UDU2q2Mau0 8rzmmRGvflz3cvUdflpK7oJj5v/u5rIp3Cm9dQEl14FUAQkLBs3akTara94wG2bc4RCA ulVg== X-Gm-Message-State: AFqh2kr0Zq+ohnEGZj22e5KC0b9UX0g4Tb1Attf6T+kSaZLOsk+9VKGE 3G/Bj0MbAfobBzvA9uVGWmP0xA== X-Google-Smtp-Source: AMrXdXsa9LCbzhYW+UV9AYutbv4orTGDloCpOs6CcMUL2eLTERixNfveBNLln72T/fHuKQXP+Tsxsg== X-Received: by 2002:a05:6512:1527:b0:4ca:f4f2:49ab with SMTP id bq39-20020a056512152700b004caf4f249abmr4081935lfb.39.1672024260274; Sun, 25 Dec 2022 19:11:00 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a12-20020a2e860c000000b0027f770526ebsm1165388lji.75.2022.12.25.19.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 19:10:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/3] phy: qualcomm: pcie2: register as clock provider Date: Mon, 26 Dec 2022 05:10:56 +0200 Message-Id: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Qualcomm QCS404 platform the PCIe2 PHY provides PIPE clock to the gcc (Global Clock Controller). Register the PHY as clock provider. Changes since v1: - Dropped 'phandle to' from supply descriptions in schema (Krzysztof), - Reordered clock-related property definitions in schema as suggested by Krzysztof, - Dropped extra empty line at the end of the schema (reported by Krzysztof). Dmitry Baryshkov (3): dt-bindings: phy: qcom,pcie2-phy: convert to YAML format phy: qualcomm: pcie2: register as clock provider arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++ .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + drivers/phy/qualcomm/phy-qcom-pcie2.c | 6 +- 4 files changed, 93 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt