From patchwork Tue Dec 6 11:23:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 631414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9371C4708C for ; Tue, 6 Dec 2022 11:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234651AbiLFLXn (ORCPT ); Tue, 6 Dec 2022 06:23:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231838AbiLFLXk (ORCPT ); Tue, 6 Dec 2022 06:23:40 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B31E2E0; Tue, 6 Dec 2022 03:23:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E248F6602AB2; Tue, 6 Dec 2022 11:23:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1670325816; bh=pflO3+JjfuOlmrDrXsHRzLY1ckIT51oZKH69uJ2/kFU=; h=From:To:Cc:Subject:Date:From; b=LeQ+CAX+P1ud0kPdsRBQmDFhAqHBbFW4Zh8RcIWbavEG1VjhQDyBLHrj0q9nfb0bH itWZKgMIxdt0/yTsPLZnfHV9TnFyqKl+9neL+agkl4WD/niF+U/gzJ/PaIyQv33QRq M9I7urg7N6pTH9lCc4iaHwp1fpSJ1spx8/YOsRi0hFDOxidhbXJv3+KGWBNvhxrG6c kl5DdLs6QjjyhA8tLTgGv0ek9um1CSjKejrSTADqVDY36Js+q+xMvAQzdQwuvYwAAP e244za1/0O3BU6v2zo1ZPqlRhnb+xJCIY/fVfCcjMO2l6yib9vUuDFwodbkqaL25wI CjkB7ECDlx2og== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, nfraprado@collabora.com, kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH 0/5] Add CPU caches information for some MediaTek SoCs Date: Tue, 6 Dec 2022 12:23:25 +0100 Message-Id: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In devicetrees for MediaTek SoCs the CPU caches information, if present, is incomplete as it misses cache size, cache line size and number of cache sets which, in turn, will also prevent any cache associativity calculation. For all of the SoCs that I know and/or I have information for, I've added the right information for I/D, L2 and L3 where present. This will also make the cacheinfo driver to correctly export the CPU cache information to sysfs. AngeloGioacchino Del Regno (5): arm64: dts: mt8195: Add complete CPU caches information arm64: dts: mt8192: Add complete CPU caches information arm64: dts: mt8186: Add complete CPU caches information arm64: dts: mt8183: Add complete CPU caches information arm64: dts: mt6795: Add complete CPU caches information arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 +++++++++++++++++++ 5 files changed, 298 insertions(+)