| Message ID | 20221121175814.68927-1-sebastian.reichel@collabora.com |
|---|---|
| Headers | show |
| Series | Initial rk3588 DT | expand |
On 21/11/2022 18:58, Sebastian Reichel wrote: > Add DT binding documentation for the Radxa Rock 5 Model A. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi, Some more things to fix... On 11/21/22 18:58, Sebastian Reichel wrote: > From: Kever Yang <kever.yang@rock-chips.com> > > This initial version supports (single core) CPU, dma, interrupts, timers, > UART and SDHCI. In short - everything necessary to boot Linux on this > system on chip. > > The DT is split into rk3588 and rk3588s, which is a reduced version > (i.e. with less peripherals) of the former. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > [rebase, squash and reword commit message] > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 + > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1722 +++++++++++++++++++++ > 2 files changed, 1784 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > new file mode 100644 > index 000000000000..dd1b66176e53 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi > @@ -0,0 +1,62 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +#include "rk3588s.dtsi" > +#include "rk3588-pinctrl.dtsi" > + > +/ { > + aliases { > + ethernet0 = &gmac0; > + }; remove > + > + gmac0: ethernet@fe1b0000 { > + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; > + reg = <0x0 0xfe1b0000 0x0 0x10000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_wake_irq"; > + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, > + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, > + <&cru CLK_GMAC0_PTP_REF>; > + clock-names = "stmmaceth", "clk_mac_ref", > + "pclk_mac", "aclk_mac", > + "ptp_ref"; > + power-domains = <&power RK3588_PD_GMAC>; > + resets = <&cru SRST_A_GMAC0>; > + reset-names = "stmmaceth"; > + rockchip,grf = <&sys_grf>; > + rockchip,php-grf = <&php_grf>; > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > + snps,mixed-burst; > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > + snps,tso; > + status = "disabled"; > + > + mdio0: mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + }; > + > + gmac0_stmmac_axi_setup: stmmac-axi-config { > + snps,blen = <0 0 0 0 16 8 4>; > + snps,wr_osr_lmt = <4>; > + snps,rd_osr_lmt = <8>; > + }; > + > + gmac0_mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <2>; > + queue0 {}; > + queue1 {}; > + }; > + > + gmac0_mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <2>; > + queue0 {}; > + queue1 {}; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > new file mode 100644 > index 000000000000..a2918a460112 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi > @@ -0,0 +1,1722 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +#include <dt-bindings/clock/rockchip,rk3588-cru.h> > +#include <dt-bindings/reset/rockchip,rk3588-cru.h> > +#include <dt-bindings/power/rk3588-power.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/irq.h> > + Sort includes. > +/ { > + compatible = "rockchip,rk3588"; > + > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + ethernet1 = &gmac1; > + gpio0 = &gpio0; > + gpio1 = &gpio1; > + gpio2 = &gpio2; > + gpio3 = &gpio3; > + gpio4 = &gpio4; > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c4 = &i2c4; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + i2c8 = &i2c8; > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + serial6 = &uart6; > + serial7 = &uart7; > + serial8 = &uart8; > + serial9 = &uart9; > + spi0 = &spi0; > + spi1 = &spi1; > + spi2 = &spi2; > + spi3 = &spi3; > + spi4 = &spi4; > + pwm0 = &pwm0; > + pwm1 = &pwm1; > + pwm2 = &pwm2; > + pwm3 = &pwm3; > + pwm4 = &pwm4; > + pwm5 = &pwm5; > + pwm6 = &pwm6; > + pwm7 = &pwm7; > + pwm8 = &pwm8; > + pwm9 = &pwm9; > + pwm10 = &pwm10; > + pwm11 = &pwm11; > + pwm12 = &pwm12; > + pwm13 = &pwm13; > + pwm14 = &pwm14; > + pwm15 = &pwm15; REMOVE ALL ALIASES FROM THIS DTSI FILE! === Bus aliases are board specific and represent what is actually available on headers/pins etc. These do not belong to SoC DTSI. Comment by Krzysztof: https://lore.kernel.org/all/f2652e0e-fb08-efb4-e25a-36a335f0c457@linaro.org/ No, not only mmc. UART, I2C, SPI - all of these should go to the board. Comment by Arnd: https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/ Each board should have its own aliases node that describes exactly which of the devices are wired up on that board, and in which order. If there are connectors on the board that are labeled in some form, then the aliases are meant to match what is written on the board or in its documentation. > + }; > + > + spll: clock-0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; Things that start with # are only needed to interpretate the DT file, so we put them down the list as possible unless they related to a perticular property. > + clock-frequency = <702000000>; > + clock-output-names = "spll"; > + }; > + > + xin24m: clock-1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + xin32k: clock-2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "xin32k"; > + }; Sort nodes without reg property in alfabetical order (including label) below somewhere near the timer node. > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu_l0>; > + }; > + core1 { > + cpu = <&cpu_l1>; > + }; > + core2 { > + cpu = <&cpu_l2>; > + }; > + core3 { > + cpu = <&cpu_l3>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&cpu_b0>; > + }; > + core1 { > + cpu = <&cpu_b1>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&cpu_b2>; > + }; > + core1 { > + cpu = <&cpu_b3>; > + }; > + }; > + }; > + > + cpu_l0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + clocks = <&scmi_clk SCMI_CLK_CPUL>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l0>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <228>; When cpus can be power and thermal trottled then add the properties needed to all cpu nodes in that group and not just to "@0". > + }; > + > + cpu_l1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x100>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + clocks = <&scmi_clk SCMI_CLK_CPUL>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l1>; > + }; > + > + cpu_l2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x200>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + clocks = <&scmi_clk SCMI_CLK_CPUL>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l2>; > + }; > + > + cpu_l3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x300>; > + enable-method = "psci"; > + capacity-dmips-mhz = <530>; > + clocks = <&scmi_clk SCMI_CLK_CPUL>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l3>; > + }; > + > + cpu_b0: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x400>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + clocks = <&scmi_clk SCMI_CLK_CPUB01>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b0>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <416>; > + }; > + > + cpu_b1: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x500>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + clocks = <&scmi_clk SCMI_CLK_CPUB01>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b1>; > + }; > + > + cpu_b2: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x600>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + clocks = <&scmi_clk SCMI_CLK_CPUB23>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b2>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <416>; > + }; > + > + cpu_b3: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,cortex-a76"; > + reg = <0x700>; > + enable-method = "psci"; > + capacity-dmips-mhz = <1024>; > + clocks = <&scmi_clk SCMI_CLK_CPUB23>; > + cpu-idle-states = <&CPU_SLEEP>; > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b3>; > + }; > + > + idle-states { > + entry-method = "psci"; > + CPU_SLEEP: cpu-sleep { > + compatible = "arm,idle-state"; > + local-timer-stop; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <100>; > + exit-latency-us = <120>; > + min-residency-us = <1000>; > + }; > + }; > + > + l2_cache_l0: l2-cache-l0 { > + compatible = "cache"; > + cache-size = <131072>; > + cache-line-size = <64>; > + cache-sets = <512>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l1: l2-cache-l1 { > + compatible = "cache"; > + cache-size = <131072>; > + cache-line-size = <64>; > + cache-sets = <512>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l2: l2-cache-l2 { > + compatible = "cache"; > + cache-size = <131072>; > + cache-line-size = <64>; > + cache-sets = <512>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l3: l2-cache-l3 { > + compatible = "cache"; > + cache-size = <131072>; > + cache-line-size = <64>; > + cache-sets = <512>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_b0: l2-cache-b0 { > + compatible = "cache"; > + cache-size = <524288>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_b1: l2-cache-b1 { > + compatible = "cache"; > + cache-size = <524288>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_b2: l2-cache-b2 { > + compatible = "cache"; > + cache-size = <524288>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_b3: l2-cache-b3 { > + compatible = "cache"; > + cache-size = <524288>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + next-level-cache = <&l3_cache>; > + }; > + > + l3_cache: l3-cache { > + compatible = "cache"; > + cache-size = <3145728>; > + cache-line-size = <64>; > + cache-sets = <4096>; > + }; > + }; > + > + pmu-a55 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pmu-a76 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + firmware { > + optee: optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + > + scmi: scmi { > + compatible = "arm,scmi-smc"; > + arm,smc-id = <0x82000010>; > + shmem = <&scmi_shmem>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + Remove empty line. > + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, > + <&scmi_clk SCMI_CLK_CPUB23>; > + assigned-clock-rates = <1200000000>, > + <1200000000>; > + }; > + > + scmi_reset: protocol@16 { > + reg = <0x16>; > + #reset-cells = <1>; > + }; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sram@10f000 { add label > + compatible = "mmio-sram"; > + reg = <0x0 0x0010f000 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x0010f000 0x100>; > + > + scmi_shmem: sram@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x100>; > + }; > + }; > + > + sys_grf: syscon@fd58c000 { > + compatible = "rockchip,rk3588-sys-grf", "syscon"; > + reg = <0x0 0xfd58c000 0x0 0x1000>; > + }; > + > + php_grf: syscon@fd5b0000 { > + compatible = "rockchip,rk3588-php-grf", "syscon"; > + reg = <0x0 0xfd5b0000 0x0 0x1000>; > + }; > + > + ioc: syscon@fd5f0000 { > + compatible = "rockchip,rk3588-ioc", "syscon"; > + reg = <0x0 0xfd5f0000 0x0 0x10000>; > + }; > + > + syssram: sram@fd600000 { sys_ram: > + compatible = "mmio-sram"; > + reg = <0x0 0xfd600000 0x0 0x100000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0xfd600000 0x100000>; > + }; > + > + cru: clock-controller@fd7c0000 { > + compatible = "rockchip,rk3588-cru"; > + reg = <0x0 0xfd7c0000 0x0 0x5c000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + assigned-clocks = > + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, > + <&cru PLL_NPLL>, <&cru PLL_GPLL>, > + <&cru ACLK_CENTER_ROOT>, > + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, > + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, > + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, > + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, > + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, > + <&cru CLK_GPU>; > + assigned-clock-rates = > + <100000000>, <786432000>, > + <850000000>, <1188000000>, > + <702000000>, > + <400000000>, <500000000>, > + <800000000>, <100000000>, > + <400000000>, <100000000>, > + <200000000>, <500000000>, > + <375000000>, <150000000>, > + <200000000>; > + rockchip,grf = <&php_grf>; > + }; > + > + i2c0: i2c@fd880000 { > + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; > + reg = <0x0 0xfd880000 0x0 0x1000>; > + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; > + clock-names = "i2c", "pclk"; > + pinctrl-0 = <&i2c0m0_xfer>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart0: serial@fd890000 { > + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xfd890000 0x0 0x100>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; > + clock-names = "baudclk", "apb_pclk"; > + dmas = <&dmac0 6>, <&dmac0 7>; dma-names = "tx", "rx"; Add dma-names for 2 or more channels with different functionality in all uart nodes. Regardless the implementation by a Linux driver. Similair to clock-names. > + pinctrl-0 = <&uart0m1_xfer>; > + pinctrl-names = "default"; > + reg-shift = <2>; > + reg-io-width = <4>; Sort these properties in all uart nodes. > + status = "disabled"; > + }; > + > + pwm0: pwm@fd8b0000 { > + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfd8b0000 0x0 0x10>; > + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm0m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm1: pwm@fd8b0010 { > + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfd8b0010 0x0 0x10>; > + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm1m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm2: pwm@fd8b0020 { > + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfd8b0020 0x0 0x10>; > + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm2m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pwm3: pwm@fd8b0030 { > + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; > + reg = <0x0 0xfd8b0030 0x0 0x10>; > + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; > + clock-names = "pwm", "pclk"; > + pinctrl-0 = <&pwm3m0_pins>; > + pinctrl-names = "active"; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + pmu: power-management@fd8d8000 { > + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; > + reg = <0x0 0xfd8d8000 0x0 0x400>; > + > + power: power-controller { > + compatible = "rockchip,rk3588-power-controller"; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + /* These power domains are grouped by VD_NPU */ > + power-domain@RK3588_PD_NPU { > + reg = <RK3588_PD_NPU>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <0>; > + > + power-domain@RK3588_PD_NPUTOP { > + reg = <RK3588_PD_NPUTOP>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&cru HCLK_NPU_ROOT>, > + <&cru PCLK_NPU_ROOT>, > + <&cru CLK_NPU_DSU0>, > + <&cru HCLK_NPU_CM0_ROOT>; > + pm_qos = <&qos_npu0_mwr>, > + <&qos_npu0_mro>, > + <&qos_mcu_npu>; > + #power-domain-cells = <0>; > + > + power-domain@RK3588_PD_NPU1 { > + reg = <RK3588_PD_NPU1>; > + clocks = <&cru HCLK_NPU_ROOT>, > + <&cru PCLK_NPU_ROOT>, > + <&cru CLK_NPU_DSU0>; > + pm_qos = <&qos_npu1>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3588_PD_NPU2 { > + reg = <RK3588_PD_NPU2>; > + clocks = <&cru HCLK_NPU_ROOT>, > + <&cru PCLK_NPU_ROOT>, > + <&cru CLK_NPU_DSU0>; > + pm_qos = <&qos_npu2>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + /* These power domains are grouped by VD_GPU */ > + power-domain@RK3588_PD_GPU { > + reg = <RK3588_PD_GPU>; > + clocks = <&cru CLK_GPU>, > + <&cru CLK_GPU_COREGROUP>, > + <&cru CLK_GPU_STACKS>; > + pm_qos = <&qos_gpu_m0>, > + <&qos_gpu_m1>, > + <&qos_gpu_m2>, > + <&qos_gpu_m3>; > + #power-domain-cells = <0>; > + }; > + /* These power domains are grouped by VD_VCODEC */ > + power-domain@RK3588_PD_VCODEC { > + reg = <RK3588_PD_VCODEC>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <0>;
Hi, This adds initial rk3588(s) DT including two different board devicetrees. All required driver changes have been merged into the respective maintainer trees. There is one warning from the DT check: $ make CHECK_DTBS=y rockchip/rk3588-evb1-v10.dtb rockchip/rk3588s-rock-5a.dtb DTC_CHK arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dtb /home/sre/src/collabora/rode/linux-rockchip-upstream/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dtb: ethernet@fe1c0000: Unevaluated properties are not allowed ('interrupt-names', 'interrupts', 'mdio', 'power-domains', 'reg', 'reset-names', 'resets', 'rx-queues-config', 'snps,axi-config', 'snps,mixed-burst', 'snps,mtl-rx-config', 'snps,mtl-tx-config', 'snps,tso', 'stmmac-axi-config', 'tx-queues-config' were unexpected) From schema: /home/sre/src/collabora/rode/linux-rockchip-upstream/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml This is for gmac1. gmac0 has the same properties and there is no warning. Also rk3588s (and thus the Rock 5A) has only gmac1 and there is no warning for the Rock 5A. It looks like for some reason the referenced "snps,dwmac.yaml#" is only checked for the first node. I think it's a bug in dt-validate. Also the same issue can be seen with rk356x. Changes since PATCHv2: * https://lore.kernel.org/all/20221115161702.163057-1-sebastian.reichel@collabora.com/ * add minimal Radxa Rock 5B DT * Add aliases for i2c, spi and gpio in rk3588s.dtsi * Fix ethernet-phy node name and remove #phy-cells * Sort nodes / includes in both boards * Sort nodes in rk3588s.dtsi according to register address * add missing spi4 node in rk3588s.dtsi * split board specific dt-bindings into their own patches * add board specific mmc alias following the downstream enumeration Changes since PATCHv1: * https://lore.kernel.org/all/20221108171500.99599-1-sebastian.reichel@collabora.com/ * Drop Acked-by from Krzysztof * Add 'regulator-' prefix to VCC12V VCC5V0 regulators * Change 'Radxa Rock 5A' to 'Radxa ROCK 5 Model A' in DT binding * Update cover-letter (clock driver and some DT binding fixes got merged) -- Sebastian Christopher Obbard (2): dt-bindings: arm: rockchip: add Rock 5 Model B arm64: dts: rockchip: Add rock-5b board Jianqun Xu (1): arm64: dts: rockchip: Add rk3588 pinctrl data Kever Yang (2): arm64: dts: rockchip: Add base DT for rk3588 SoC arm64: dts: rockchip: Add rk3588-evb1 board Sebastian Reichel (4): dt-bindings: soc: rockchip: add initial rk3588 syscon compatibles dt-bindings: arm: rockchip: add RK3588 EVB1 dt-bindings: arm: rockchip: add Rock 5 Model A arm64: dts: rockchip: Add rock-5a board .../devicetree/bindings/arm/rockchip.yaml | 15 + .../devicetree/bindings/soc/rockchip/grf.yaml | 5 + arch/arm64/boot/dts/rockchip/Makefile | 3 + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 159 + .../boot/dts/rockchip/rk3588-pinctrl.dtsi | 516 +++ .../boot/dts/rockchip/rk3588-rock-5b.dts | 43 + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 + .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++ .../boot/dts/rockchip/rk3588s-rock-5a.dts | 66 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1722 +++++++++ 10 files changed, 5994 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi