| Message ID | 20221121041757.418645-1-uwu@icenowy.me |
|---|---|
| Headers | show |
| Series | Some DT binding quirks for T-Head C9xx | expand |
在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道： > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > compliant to the newcoming ACLINT spec) because of lack of mtime > register. > > Add a compatible string formatted like the C9xx-specific PLIC > compatible, and do not allow a SiFive one as fallback because they're > not really compliant. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Hi, could this patch be picked ASAP? Becuase it will be used then in further OpenSBI patches to enable proper operation of T-Head timer. I know the following 2 patches are in doubt and further rework for them are needed. > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 > ++++++++ > 1 file changed, 8 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index bbad24165837..aada6957216c 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -20,6 +20,10 @@ description: > property of "/cpus" DT node. The "timebase-frequency" DT property > is > described in Documentation/devicetree/bindings/riscv/cpus.yaml > > + T-Head C906/C910 CPU cores include an implementation of CLINT too, > however > + their implementation lacks a memory-mapped MTIME register, thus > not > + compatible with SiFive ones. > + > properties: > compatible: > oneOf: > @@ -29,6 +33,10 @@ properties: > - starfive,jh7100-clint > - canaan,k210-clint > - const: sifive,clint0 > + - items: > + - enum: > + - allwinner,sun20i-d1-clint > + - const: thead,c900-clint > - items: > - const: sifive,clint0 > - const: riscv,clint0
On Wed, Dec 07, 2022 at 06:47:26PM +0800, Icenowy Zheng wrote: > 在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道： > > T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not > > compliant to the newcoming ACLINT spec) because of lack of mtime > > register. > > > > Add a compatible string formatted like the C9xx-specific PLIC > > compatible, and do not allow a SiFive one as fallback because they're > > not really compliant. > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > Hi, could this patch be picked ASAP? Becuase it will be used then in > further OpenSBI patches to enable proper operation of T-Head timer. > > I know the following 2 patches are in doubt and further rework for them > are needed. Since it's me that's asking the questions about the other patches, but have no comments about this particular one: Acked-by: Conor Dooley <conor.dooley@microchip.com> HTH Icenowy! > > --- > > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 > > ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > index bbad24165837..aada6957216c 100644 > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -20,6 +20,10 @@ description: > > property of "/cpus" DT node. The "timebase-frequency" DT property > > is > > described in Documentation/devicetree/bindings/riscv/cpus.yaml > > > > + T-Head C906/C910 CPU cores include an implementation of CLINT too, > > however > > + their implementation lacks a memory-mapped MTIME register, thus > > not > > + compatible with SiFive ones. > > + > > properties: > > compatible: > > oneOf: > > @@ -29,6 +33,10 @@ properties: > > - starfive,jh7100-clint > > - canaan,k210-clint > > - const: sifive,clint0 > > + - items: > > + - enum: > > + - allwinner,sun20i-d1-clint > > + - const: thead,c900-clint > > - items: > > - const: sifive,clint0 > > - const: riscv,clint0 > >
These patchset is just full of DT binding patches related to T-Head C906/C910. These cores now have an open-source fixed-configuration edition, which enables everyone to explore with them. The first patch adds an compatible string set for T-Head CLINT, which is incompatible with SiFive ones by not having a mtime register. The Linux CLINT driver, which is only used in M mode now, does not support it at all -- having a DT binding is for OpenSBI. The second and third patches are for OpenC906, the open source edition of C906. They try to add some DT binding strings for it. By the way, as we discussed in the BoufalloLab series, C906/C910 do not have so many customizable options for PLIC/CLINT, so maybe we should not add additional per-SoC-system compatible strings and allow only "thead,c900-*". Icenowy Zheng (3): dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx dt-bindings: timer: sifive,clint: add compatible for OpenC906 dt-bindings: interrupt-controller: sifive,plic: add OpenC906 compatible .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/timer/sifive,clint.yaml | 9 +++++++++ 2 files changed, 10 insertions(+)