| Message ID | 20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add IRQC support to RZ/G2UL SoC | expand |
Hi Prabhakar, On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add required properties in pinctrl node to handle GPIO interrupts. > > Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent > is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver > continues without waiting for IRQC to probe. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi > @@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 { > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&pinctrl 0 0 152>; > + #interrupt-cells = <2>; > + interrupt-controller; > clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; > power-domains = <&cpg>; > resets = <&cpg R9A07G043_GPIO_RSTN>, > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > index 7a8ed7ae253b..65e7b029361e 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > @@ -98,6 +98,10 @@ &irqc { > resets = <&cpg R9A07G043_IA55_RESETN>; > }; > > +&pinctrl { > + interrupt-parent = <&irqc>; > +}; Do you plan to move it back to the common r9a07g043.dtsi later? Perhaps it makes sense to move the full irqc node to r9a07g043[uf].dtsi? There is not that much common left, even the compatible value differs. We don't keep the few common properties of the cpu0 node in r9a07g043.dtsi neither. > + > &soc { > interrupt-parent = <&gic>; > Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thu, Nov 17, 2022 at 10:54 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is > > identical to one found on the RZ/G2L SoC. No driver changes are > > required as generic compatible string "renesas,rzg2l-irqc" will be > > used as a fallback. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- > > Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five > > - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt > > domain) -> RISCV INTC > > I think this difference is purely a software difference, and abstracted > in DTS through the interrupt hierarchy. > Does it have any impact on the bindings? > > > - On the RZ/Five we have additional registers for IRQC block > > Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus > warranting separate compatible values. > > > - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC > > Can you please elaborate? I may have missed something, but to me it > looks like that is exactly the same on RZ/G2UL and on RZ/Five. > Now that we have to update the binding doc with the BUS_ERR_INT too, do you think it would make sense to add interrupt-names too? BUS_ERR_INT will have to be handled IRQC itself (i.e. IRQC will register a handler for it). Cheers, Prabhakar
Hi Geert, On Fri, Nov 18, 2022 at 12:29 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Geert, > > On Thu, Nov 17, 2022 at 10:54 AM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > > > Hi Prabhakar, > > > > On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is > > > identical to one found on the RZ/G2L SoC. No driver changes are > > > required as generic compatible string "renesas,rzg2l-irqc" will be > > > used as a fallback. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- > > > Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five > > > - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt > > > domain) -> RISCV INTC > > > > I think this difference is purely a software difference, and abstracted > > in DTS through the interrupt hierarchy. > > Does it have any impact on the bindings? > > > > > - On the RZ/Five we have additional registers for IRQC block > > > > Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus > > warranting separate compatible values. > > > > > - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC > > > > Can you please elaborate? I may have missed something, but to me it > > looks like that is exactly the same on RZ/G2UL and on RZ/Five. > > > Now that we have to update the binding doc with the BUS_ERR_INT too, > do you think it would make sense to add interrupt-names too? > > BUS_ERR_INT will have to be handled IRQC itself (i.e. IRQC will > register a handler for it). > Gentle ping. Cheers, Prabhakar
Hi Prabhakar, On Mon, Dec 19, 2022 at 1:57 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Fri, Nov 18, 2022 at 12:29 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Nov 17, 2022 at 10:54 AM Geert Uytterhoeven > > <geert@linux-m68k.org> wrote: > > > On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Document RZ/G2UL (R9A07G043) IRQC bindings. The RZ/G2UL IRQC block is > > > > identical to one found on the RZ/G2L SoC. No driver changes are > > > > required as generic compatible string "renesas,rzg2l-irqc" will be > > > > used as a fallback. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Note, renesas,r9a07g043u-irqc is added we have slight difference's compared to RZ/Five > > > > - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt > > > > domain) -> RISCV INTC > > > > > > I think this difference is purely a software difference, and abstracted > > > in DTS through the interrupt hierarchy. > > > Does it have any impact on the bindings? > > > > > > > - On the RZ/Five we have additional registers for IRQC block > > > > > > Indeed, the NMI/IRQ/TINT "Interruput" Mask Control Registers, thus > > > warranting separate compatible values. > > > > > > > - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC > > > > > > Can you please elaborate? I may have missed something, but to me it > > > looks like that is exactly the same on RZ/G2UL and on RZ/Five. > > > > > Now that we have to update the binding doc with the BUS_ERR_INT too, > > do you think it would make sense to add interrupt-names too? > Gentle ping. Thanks for the ping, I had missed you were waiting on input from me. Sorry for that... As there are three different groups of parent interrupts, adding interrupt-names makes sense. However, as this binding is already in active use since v6.1, you probably need to keep on supporting the ack of interrupt-names. Or do you think there are no real users yet, and we can drop support for that? > > BUS_ERR_INT will have to be handled IRQC itself (i.e. IRQC will > > register a handler for it). Do you mean you will need a fourth parent type for that? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, This patch series does the following: * Adds IRQC support to the RZ/G2UL SoC. * Includes a fix for pinctrl driver when using GPIO pins as interrupts * Adds PHY interrupt support for ETH{0/1} Reason for sending it as RFC, as I am introducing new compatible string for RZ/G2UL SoC as there are some differences when compared to RZ/Five: - G2UL IRQCHIP (hierarchical IRQ domain) -> GIC where as on RZ/Five we have PLIC (chained interrupt domain) -> RISCV INTC - On the RZ/Five we have additional registers for IRQC block - On the RZ/Five we have BUS_ERR_INT which needs to be handled by IRQC Cheers, Prabhakar Lad Prabhakar (5): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts arm64: dts: renesas: r9a07g043[u]: Add IRQC node arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} .../renesas,rzg2l-irqc.yaml | 1 + arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 10 ++++ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 54 +++++++++++++++++++ .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +++--- 5 files changed, 84 insertions(+), 9 deletions(-)