| Message ID | 20220923202911.119729-1-gerhard@engleder-embedded.com |
|---|---|
| Headers | show |
| Series | tsnep: multi queue support and some other improvements | expand |
Fix the following dtbs_check error if dma-coherent is used: ...: 'dma-coherent' does not match any of the regexes: 'pinctrl-[0-9]+'
On 23/09/2022 22:29, Gerhard Engleder wrote: > Fix the following dtbs_check error if dma-coherent is used: > > ...: 'dma-coherent' does not match any of the regexes: 'pinctrl-[0-9]+' > From schema: .../Documentation/devicetree/bindings/net/engleder,tsnep.yaml Skip last line - it's obvious. What instead you miss here - the DTS/target which has this warning. I assume that some existing DTS uses this property? > > Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> Best regards, Krzysztof
On 23/09/2022 22:29, Gerhard Engleder wrote: > Additional TX/RX queue pairs require dedicated interrupts. Extend > binding with additional interrupts. > > Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> > --- > .../bindings/net/engleder,tsnep.yaml | 37 ++++++++++++++++++- > 1 file changed, 36 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml > index 37e08ee744a8..ce1f1bd413c2 100644 > --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml > +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml > @@ -20,7 +20,23 @@ properties: > maxItems: 1 > > interrupts: > - maxItems: 1 > + minItems: 1 > + maxItems: 8 > + > + interrupt-names: > + minItems: 1 > + maxItems: 8 > + items: > + pattern: '^mac|txrx-[1-7]$' No. The order of items must be fixed. Now you allow any combination, which is exactly what we do not want. > + description: > + If more than one interrupt is available, then interrupts are > + identified by their names. Not really. Interrupts are fixed, unless explicitly mentioned otherwise. > + "mac" is the main interrupt for basic MAC features and the first > + TX/RX queue pair. If only a single interrupt is available, then > + it is assumed that this interrupt is the "mac" interrupt. > + "txrx-[1-7]" are the interrupts for additional TX/RX queue pairs. > + These interrupt names shall start with index 1 and increment the > + index by 1 with every further TX/RX queue pair. Skip last three sentences - they will become redundant after implementing proper items. > > dma-coherent: true > > @@ -78,4 +94,23 @@ examples: > }; > }; > }; Missing line break. Best regards, Krzysztof
On 24.09.22 11:15, Krzysztof Kozlowski wrote: > On 23/09/2022 22:29, Gerhard Engleder wrote: >> Fix the following dtbs_check error if dma-coherent is used: >> >> ...: 'dma-coherent' does not match any of the regexes: 'pinctrl-[0-9]+' >> From schema: .../Documentation/devicetree/bindings/net/engleder,tsnep.yaml > > Skip last line - it's obvious. What instead you miss here - the > DTS/target which has this warning. I assume that some existing DTS uses > this property? I will skip that line. The binding is for an FPGA based Ethernet MAC. I'm working with an evaluation platform currently. The DTS for the evaluation platform is mainline, but my derived DTS was not accepted mainline. So there is no DTS. This is similar for other FPGA based devices. >> >> Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> > Best regards, > Krzysztof Thanks! Gerhard
On 24.09.22 11:17, Krzysztof Kozlowski wrote: > On 23/09/2022 22:29, Gerhard Engleder wrote: >> Additional TX/RX queue pairs require dedicated interrupts. Extend >> binding with additional interrupts. >> >> Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> >> --- >> .../bindings/net/engleder,tsnep.yaml | 37 ++++++++++++++++++- >> 1 file changed, 36 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml >> index 37e08ee744a8..ce1f1bd413c2 100644 >> --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml >> +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml >> @@ -20,7 +20,23 @@ properties: >> maxItems: 1 >> >> interrupts: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 8 >> + >> + interrupt-names: >> + minItems: 1 >> + maxItems: 8 >> + items: >> + pattern: '^mac|txrx-[1-7]$' > > No. The order of items must be fixed. Now you allow any combination, > which is exactly what we do not want. Ok. I will do it like in https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml#L58 >> + description: >> + If more than one interrupt is available, then interrupts are >> + identified by their names. > > Not really. Interrupts are fixed, unless explicitly mentioned otherwise. > >> + "mac" is the main interrupt for basic MAC features and the first >> + TX/RX queue pair. If only a single interrupt is available, then >> + it is assumed that this interrupt is the "mac" interrupt. >> + "txrx-[1-7]" are the interrupts for additional TX/RX queue pairs. >> + These interrupt names shall start with index 1 and increment the >> + index by 1 with every further TX/RX queue pair. > > Skip last three sentences - they will become redundant after > implementing proper items. I will rework description for fixed order. >> >> dma-coherent: true >> >> @@ -78,4 +94,23 @@ examples: >> }; >> }; >> }; > > Missing line break. I will add it. > Best regards, > Krzysztof Thanks! Gerhard
On 26/09/2022 19:46, Gerhard Engleder wrote: >> That would be okay, but please add answer to why you are making this change. > > I already prepared it: > > Within SoCs like ZynqMP, FPGA logic can be connected to different kinds > of AXI master ports. Also cache coherent AXI master ports are available. > The property "dma-coherent" is used to signal that DMA is cache > coherent. > Add "dma-coherent" property to allow the configuration of cache coherent > DMA. > Sounds good, thanks. Best regards, Krzysztof