| Message ID | 20220915163947.1922183-1-jagan@edgeble.ai |
|---|---|
| Headers | show |
| Series | ARM: Add Rockchip RV1126 support | expand |
Hi Jagan, Am Donnerstag, 15. September 2022, 18:39:46 CEST schrieb Jagan Teki: > Add pinctrl definitions for Rockchip RV1126 and the pinctrl > conf's are included it from arm64 rockchip devicetree path. I'm not sure I remember the cause. So could you tell me why they are needed in the arm64-space as well? Thanks Heiko > Signed-off-by: Jagan Teki <jagan@edgeble.ai> > --- > Changes for v5: > - none > Changes for v4: > - update i2c pins > - rebase on -next > Changes for v3: > - none > Changes for v2: > - spilt pinctrl as separate patch > > MAINTAINERS | 2 +- > arch/arm/boot/dts/rv1126-pinctrl.dtsi | 212 ++++++++++++++++++++++++++ > 2 files changed, 213 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9d7f64dc0efe..9ddb45285676 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -2690,7 +2690,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml > F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml > F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml > F: arch/arm/boot/dts/rk3* > -F: arch/arm/boot/dts/rv1108* > +F: arch/arm/boot/dts/rv11* > F: arch/arm/mach-rockchip/ > F: drivers/*/*/*rockchip* > F: drivers/*/*rockchip* > diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi > new file mode 100644 > index 000000000000..8d660d7c81ba > --- /dev/null > +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi > @@ -0,0 +1,212 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd > + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. > + */ > + > +#include <dt-bindings/pinctrl/rockchip.h> > +#include <arm64/rockchip/rockchip-pinconf.dtsi> > + > +/* > + * This file is auto generated by pin2dts tool, please keep these code > + * by adding changes at end of this file. > + */ > +&pinctrl { > + emmc { > + /omit-if-no-ref/ > + emmc_rstnout: emmc-rstnout { > + rockchip,pins = > + /* emmc_rstn */ > + <1 RK_PA3 2 &pcfg_pull_none>; > + }; > + /omit-if-no-ref/ > + emmc_bus8: emmc-bus8 { > + rockchip,pins = > + /* emmc_d0 */ > + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d1 */ > + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d2 */ > + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d3 */ > + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d4 */ > + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d5 */ > + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d6 */ > + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, > + /* emmc_d7 */ > + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + emmc_clk: emmc-clk { > + rockchip,pins = > + /* emmc_clko */ > + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + emmc_cmd: emmc-cmd { > + rockchip,pins = > + /* emmc_cmd */ > + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; > + }; > + }; > + i2c0 { > + /omit-if-no-ref/ > + i2c0_xfer: i2c0-xfer { > + rockchip,pins = > + /* i2c0_scl */ > + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, > + /* i2c0_sda */ > + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; > + }; > + }; > + sdmmc0 { > + /omit-if-no-ref/ > + sdmmc0_bus4: sdmmc0-bus4 { > + rockchip,pins = > + /* sdmmc0_d0 */ > + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc0_d1 */ > + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc0_d2 */ > + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc0_d3 */ > + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc0_clk: sdmmc0-clk { > + rockchip,pins = > + /* sdmmc0_clk */ > + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc0_cmd: sdmmc0-cmd { > + rockchip,pins = > + /* sdmmc0_cmd */ > + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc0_det: sdmmc0-det { > + rockchip,pins = > + <0 RK_PA3 1 &pcfg_pull_none>; > + }; > + /omit-if-no-ref/ > + sdmmc0_pwr: sdmmc0-pwr { > + rockchip,pins = > + <0 RK_PC0 1 &pcfg_pull_none>; > + }; > + }; > + sdmmc1 { > + /omit-if-no-ref/ > + sdmmc1_bus4: sdmmc1-bus4 { > + rockchip,pins = > + /* sdmmc1_d0 */ > + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc1_d1 */ > + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc1_d2 */ > + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, > + /* sdmmc1_d3 */ > + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc1_clk: sdmmc1-clk { > + rockchip,pins = > + /* sdmmc1_clk */ > + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc1_cmd: sdmmc1-cmd { > + rockchip,pins = > + /* sdmmc1_cmd */ > + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; > + }; > + /omit-if-no-ref/ > + sdmmc1_det: sdmmc1-det { > + rockchip,pins = > + <1 RK_PD0 2 &pcfg_pull_none>; > + }; > + /omit-if-no-ref/ > + sdmmc1_pwr: sdmmc1-pwr { > + rockchip,pins = > + <1 RK_PD1 2 &pcfg_pull_none>; > + }; > + }; > + uart0 { > + /omit-if-no-ref/ > + uart0_xfer: uart0-xfer { > + rockchip,pins = > + /* uart0_rx */ > + <1 RK_PC2 1 &pcfg_pull_up>, > + /* uart0_tx */ > + <1 RK_PC3 1 &pcfg_pull_up>; > + }; > + /omit-if-no-ref/ > + uart0_ctsn: uart0-ctsn { > + rockchip,pins = > + <1 RK_PC1 1 &pcfg_pull_none>; > + }; > + /omit-if-no-ref/ > + uart0_rtsn: uart0-rtsn { > + rockchip,pins = > + <1 RK_PC0 1 &pcfg_pull_none>; > + }; > + /omit-if-no-ref/ > + uart0_rtsn_gpio: uart0-rts-pin { > + rockchip,pins = > + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + uart1 { > + /omit-if-no-ref/ > + uart1m0_xfer: uart1m0-xfer { > + rockchip,pins = > + /* uart1_rx_m0 */ > + <0 RK_PB7 2 &pcfg_pull_up>, > + /* uart1_tx_m0 */ > + <0 RK_PB6 2 &pcfg_pull_up>; > + }; > + }; > + uart2 { > + /omit-if-no-ref/ > + uart2m1_xfer: uart2m1-xfer { > + rockchip,pins = > + /* uart2_rx_m1 */ > + <3 RK_PA3 1 &pcfg_pull_up>, > + /* uart2_tx_m1 */ > + <3 RK_PA2 1 &pcfg_pull_up>; > + }; > + }; > + uart3 { > + /omit-if-no-ref/ > + uart3m0_xfer: uart3m0-xfer { > + rockchip,pins = > + /* uart3_rx_m0 */ > + <3 RK_PC7 4 &pcfg_pull_up>, > + /* uart3_tx_m0 */ > + <3 RK_PC6 4 &pcfg_pull_up>; > + }; > + }; > + uart4 { > + /omit-if-no-ref/ > + uart4m0_xfer: uart4m0-xfer { > + rockchip,pins = > + /* uart4_rx_m0 */ > + <3 RK_PA5 4 &pcfg_pull_up>, > + /* uart4_tx_m0 */ > + <3 RK_PA4 4 &pcfg_pull_up>; > + }; > + }; > + uart5 { > + /omit-if-no-ref/ > + uart5m0_xfer: uart5m0-xfer { > + rockchip,pins = > + /* uart5_rx_m0 */ > + <3 RK_PA7 4 &pcfg_pull_up>, > + /* uart5_tx_m0 */ > + <3 RK_PA6 4 &pcfg_pull_up>; > + }; > + }; > +}; >
Hi Heiko, On Sat, 17 Sept 2022 at 19:56, Heiko Stuebner <heiko@sntech.de> wrote: > > Hi Jagan, > > Am Donnerstag, 15. September 2022, 18:39:46 CEST schrieb Jagan Teki: > > Add pinctrl definitions for Rockchip RV1126 and the pinctrl > > conf's are included it from arm64 rockchip devicetree path. > > I'm not sure I remember the cause. So could you tell me > why they are needed in the arm64-space as well?
On Thu, 15 Sep 2022 22:09:41 +0530, Jagan Teki wrote: > RV1126 is a high-performance vision processor SoC for IPC/CVR, > especially for AI related application. > > This series add left over patches from v4 [1]. The dts patches > will send in another series as we have some naming convention > updates. > > [...] Applied, thanks! [2/6] clk: rockchip: Add dt-binding header for RV1126 commit: bc35a430dfde16462feb4428bc9b42c0647b5b84 [3/6] dt-bindings: clock: rockchip: Document RV1126 CRU commit: a1f65e64c6a3aa920b059aba5c97598cc0d17978 [4/6] clk: rockchip: Add clock controller support for RV1126 SoC. commit: 7f2f620daa88e72b04efd2f3da84abea0b5ca1c7 Best regards,
From: Jagan Teki <jagan@amarulasolutions.com> RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. This series add left over patches from v4 [1]. The dts patches will send in another series as we have some naming convention updates. [1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220907160207.3845791-1-jagan@edgeble.ai/ Any inputs? Jagan. Jagan Teki (6): i2c: rk3x: Add rv1126 support clk: rockchip: Add dt-binding header for RV1126 dt-bindings: clock: rockchip: Document RV1126 CRU clk: rockchip: Add clock controller support for RV1126 SoC. ARM: dts: rockchip: Add Rockchip RV1126 pinctrl ARM: dts: rockchip: Add Rockchip RV1126 SoC .../bindings/clock/rockchip,rv1126-cru.yaml | 62 + MAINTAINERS | 2 +- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 212 +++ arch/arm/boot/dts/rv1126.dtsi | 430 ++++++ drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rv1126.c | 1156 +++++++++++++++++ drivers/clk/rockchip/clk.h | 19 + drivers/i2c/busses/i2c-rk3x.c | 9 + .../dt-bindings/clock/rockchip,rv1126-cru.h | 632 +++++++++ 10 files changed, 2529 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/rv1126.dtsi create mode 100644 drivers/clk/rockchip/clk-rv1126.c create mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h