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[v2,0/2] Renesas Versaclock7 Bindings and Clock Driver

Message ID 20220912183613.22213-1-alexander.helms.jy@renesas.com
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Series Renesas Versaclock7 Bindings and Clock Driver | expand

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Alex Helms Sept. 12, 2022, 6:36 p.m. UTC 
Device tree bindings and a common clock framework device driver
for the Renesas VersaClock7 clock generator family.
---
Changelog v2:
- Index to output number varies based on which VC7 chip model is used.
  Correct bank to output reference requires converting index to output number
  based on chip model.
- Differentiate between multiple instance of clock nodes by using
  the value of 'clock-output-names' property.

Alex Helms (2):
  dt-bindings: Renesas versaclock7 device tree bindings
  clk: Renesas versaclock7 ccf device driver

 .../bindings/clock/renesas,versaclock7.yaml   |   64 +
 MAINTAINERS                                   |    6 +
 drivers/clk/Kconfig                           |    9 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/clk-versaclock7.c                 | 1292 +++++++++++++++++
 5 files changed, 1372 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
 create mode 100755 drivers/clk/clk-versaclock7.c


base-commit: f443e374ae131c168a065ea1748feac6b2e76613