mbox series

[00/11] Improvements to the Qcom PCIe Endpoint driver

Message ID 20220826181923.251564-1-manivannan.sadhasivam@linaro.org
Headers show
Series Improvements to the Qcom PCIe Endpoint driver | expand

Message

Manivannan Sadhasivam Aug. 26, 2022, 6:19 p.m. UTC 
Hello,

This series contains improvements to the Qualcomm PCIe Endpoint controller
driver. The major improvements are the addition of SM8450 SoC support and
debugfs interface for exposing link transition counts.

This series has been tested on SM8450 based dev board.

Thanks,
Mani

Manivannan Sadhasivam (11):
  PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure
  PCI: qcom-ep: Do not use hardcoded clks in driver
  PCI: qcom-ep: Make use of the cached dev pointer
  PCI: qcom-ep: Add eDMA support
  PCI: qcom-ep: Disable IRQs during driver remove
  PCI: qcom-ep: Add debugfs support for expose link transition counts
  dt-bindings: PCI: qcom-ep: Make PERST separation optional
  PCI: qcom-ep: Make PERST separation optional
  dt-bindings: PCI: qcom-ep: Define clocks per platform
  dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC
  PCI: qcom-ep: Add support for SM8450 SoC

 .../devicetree/bindings/pci/qcom,pcie-ep.yaml |  70 ++++++---
 drivers/pci/controller/dwc/pcie-qcom-ep.c     | 140 ++++++++++++++----
 2 files changed, 159 insertions(+), 51 deletions(-)

Comments

Manivannan Sadhasivam Aug. 30, 2022, 11:56 a.m. UTC | #1 
On Sun, Aug 28, 2022 at 06:20:21PM +0300, Krzysztof Kozlowski wrote:
> On 26/08/2022 21:19, Manivannan Sadhasivam wrote:
> > In preparation of adding the bindings for future SoCs, let's define the
> > clocks per platform.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 46 +++++++++++--------
> >  1 file changed, 27 insertions(+), 19 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > index b728ede3f09f..83a2cfc63bc1 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > @@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding
> >  maintainers:
> >    - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >  
> > -allOf:
> > -  - $ref: "pci-ep.yaml#"
> > -
> >  properties:
> >    compatible:
> >      const: qcom,sdx55-pcie-ep
> > @@ -35,24 +32,12 @@ properties:
> >        - const: mmio
> >  
> >    clocks:
> > -    items:
> > -      - description: PCIe Auxiliary clock
> > -      - description: PCIe CFG AHB clock
> > -      - description: PCIe Master AXI clock
> > -      - description: PCIe Slave AXI clock
> > -      - description: PCIe Slave Q2A AXI clock
> > -      - description: PCIe Sleep clock
> > -      - description: PCIe Reference clock
> > +    minItems: 7
> > +    maxItems: 7
> >  
> >    clock-names:
> > -    items:
> > -      - const: aux
> > -      - const: cfg
> > -      - const: bus_master
> > -      - const: bus_slave
> > -      - const: slave_q2a
> > -      - const: sleep
> > -      - const: ref
> > +    minItems: 7
> > +    maxItems: 7
> >  
> >    qcom,perst-regs:
> >      description: Reference to a syscon representing TCSR followed by the two
> > @@ -112,6 +97,29 @@ required:
> >    - reset-names
> >    - power-domains
> >  
> > +allOf:
> > +  - $ref: "pci-ep.yaml#"
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - qcom,sdx55-pcie-ep
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 7
> > +          maxItems: 7
> 
> One more thing - the previous way of describing items is more readable
> instead of names followed by a comment, so I propose to keep it. This
> applies also to patch 10.
> 

Okay.

Thanks,
Mani

> Best regards,
> Krzysztof