From patchwork Thu Aug 25 18:04:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 600103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CCA4ECAA25 for ; Thu, 25 Aug 2022 18:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243018AbiHYSFa (ORCPT ); Thu, 25 Aug 2022 14:05:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242980AbiHYSF2 (ORCPT ); Thu, 25 Aug 2022 14:05:28 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1123072EDF for ; Thu, 25 Aug 2022 11:05:27 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id s23so10594606wmj.4 for ; Thu, 25 Aug 2022 11:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc; bh=JUTRY4gaK8Gdeip+jNVieK44Ohhk3yQH8niH5zENkSw=; b=UQRwsSKSQOopSzPEnfGl08Wcz8NArorGUNMK0W1lv9/M3NFHsrXasUoP/8N6hnNLyh Db+QzkVDzRMXC3hgUyXq0p/ra8hm2s0axZjgkn5/xzjO73xUBq3NWFs8zslI3FobG/9q ElabZvviGU6oh6mONYgE7ezidVx0xJSjXX7zA3rtbmtllF1f27STAnj3DnA+VfAXUkMl Da7Z8W1c5erVgM2O39G0VW5VS1MZds4EV6uliQXvj/E8xFQyQSOgSyjZyifITgzLG8Ka oMAd0Sich0b0OCAAyxB0J9XknMkajEdI82BQg3Gwbo/HoD4VPnFnOKOAkEkcJMZH3M23 2JKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc; bh=JUTRY4gaK8Gdeip+jNVieK44Ohhk3yQH8niH5zENkSw=; b=A4q+J2MacptvBi/Hi+uzxI3yXLsilCtr4kWl+5duFRsova4P2mtKnLwcCDA+Wn7die 0DE2yUoUD0MDcLmPhh2dnuxlcnR/3bIDDIRKgfgw/qe6T2LZ0pQ4ia3otqIJx+Ipuk0i Rb0FXTGd+5WFRPxRIvrmWFD7DoGp32G1ETSm5lbgvilrJDVMaXZ0mVpwc7Bm89NGJAQk 6reiVEZbccfJmHlOBl5TcjsTQ7r5Me9kZy8Xzn+3MklKGBGVOknOwkL7JQQMNs6HiNQ1 +yi7NiYFgQpfa4bIK0U7i7TL3hIE+Psy7OraezAkyfRRtIT3vJ5et5rwR7M4FDxAAryF QtLw== X-Gm-Message-State: ACgBeo0t/koa7B61RAJuMrIdrLrfVifstS72N9X5knyjS1ZSbtCi3vw5 fB2OB4khrf2P+4zjKSSBbn2LyQ== X-Google-Smtp-Source: AA6agR5biMHZOOviA7RBIh8sODjlp+ZpN4gWA6662c/obgpPYUJW3Xon/lSc/ip8BcNFU0lBj4jAww== X-Received: by 2002:a05:600c:3d09:b0:3a5:e408:ca19 with SMTP id bh9-20020a05600c3d0900b003a5e408ca19mr3121650wmb.135.1661450725527; Thu, 25 Aug 2022 11:05:25 -0700 (PDT) Received: from henark71.. ([51.37.149.245]) by smtp.gmail.com with ESMTPSA id j4-20020a5d6044000000b002254a7f4b9csm14967970wrt.48.2022.08.25.11.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 11:05:25 -0700 (PDT) From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou , Conor Dooley , Daire McNamara Cc: Sagar Kadam , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/2] Add a PolarFire SoC l2 compatible Date: Thu, 25 Aug 2022 19:04:16 +0100 Message-Id: <20220825180417.1259360-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Whilst re-running checks before sending my dt-fixes PR today I noticed that I had introduced another dtbs_check warning by applying one of the patches in it. PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts re-uses the compatible of currently) which only has 3. Add a new string to the binding like should've been done in the first place... The driver does not care which compatible it matches against, and just uses as many interrupts as are in the dts so will happily work away without any needed changes there. @Palmer, you can take this directly as long as my fixes PR for rc3 is merged if you like, since the application path for the binding is via you anyway. I suppose I could take both too, but whatever works best for you (: Thanks, Conor. Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 2 files changed, 50 insertions(+), 31 deletions(-) Reviewed-by: Rob Herring