| Message ID | 20220825180417.1259360-1-mail@conchuod.ie |
|---|---|
| Headers | show |
| Series | Add a PolarFire SoC l2 compatible | expand |
On Thu, Aug 25, 2022 at 1:36 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > On 8/25/22 20:04, Conor Dooley wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > > the fu740. It has the extra interrupt from the fu740 but the lower > > number of cache-sets. Add a specific compatible to avoid the likes > > of: > > > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long > > Where is such a message written? I couldn't find the string in > next-20220825 (git grep -n 'is too long"'). > > Why should a different number of cache sets require an extra compatible > string. cache-size is simply a parameter going with the existing > compatible strings. > > I would assume that you only need an extra compatible string if there is > a functional difference that can not be expressed with the existing > parameters. Correct, but you have to account for unknown functional differences aka errata as well. Otherwise, we need firmware updates to enable the OS to handle errata. > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > > 1 file changed, 49 insertions(+), 30 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > index 69cdab18d629..ca3b9be58058 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > @@ -17,9 +17,6 @@ description: > > acts as directory-based coherency manager. > > All the properties in ePAPR/DeviceTree specification applies for this platform. > > > > -allOf: > > - - $ref: /schemas/cache-controller.yaml# > > - > > select: > > properties: > > compatible: > > @@ -33,11 +30,16 @@ select: > > > > properties: > > compatible: > > - items: > > - - enum: > > - - sifive,fu540-c000-ccache > > - - sifive,fu740-c000-ccache > > Why can't you simply add microchip,mpfs-ccache here? > > > - - const: cache > > + oneOf: > > + - items: > > + - enum: > > + - sifive,fu540-c000-ccache > > + - sifive,fu740-c000-ccache > > + - const: cache > > + - items: > > + - const: microchip,mpfs-ccache > > + - const: sifive,fu540-c000-ccache > > Why do we need 'sifive,fu540-c000-ccache' twice? Because it is in 2 different positions. While we can express that the last N entries in a list are optional, there is no way in json-schema to express entries at the beginning or in the middle are optional. Rob
On Thu, 25 Aug 2022 19:04:17 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The l2 cache on PolarFire SoC is cross between that of the fu540 and > the fu740. It has the extra interrupt from the fu740 but the lower > number of cache-sets. Add a specific compatible to avoid the likes > of: > > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long > > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- > 1 file changed, 49 insertions(+), 30 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
From: Conor Dooley <conor.dooley@microchip.com> On Thu, 25 Aug 2022 19:04:16 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Whilst re-running checks before sending my dt-fixes PR today I noticed > that I had introduced another dtbs_check warning by applying one of the > patches in it. > > PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts > re-uses the compatible of currently) which only has 3. Add a new string > to the binding like should've been done in the first place... > > [...] @Palmer, I have applied these to my dt-fixes, branch as the commit they fix is there too. As I mentioned on IRC, patches for this dt-binding are usually merged via the riscv tree so I have taken the liberty of bundling it with the dts change. You may get this in a PR friday morning, but more likely early next week. Conor. [1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible https://git.kernel.org/conor/c/17e4732d1d8a [2/2] riscv: dts: microchip: use an mpfs specific l2 compatible https://git.kernel.org/conor/c/0dec364ffeb6 Thanks, Conor.
From: Conor Dooley <conor.dooley@microchip.com> Whilst re-running checks before sending my dt-fixes PR today I noticed that I had introduced another dtbs_check warning by applying one of the patches in it. PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts re-uses the compatible of currently) which only has 3. Add a new string to the binding like should've been done in the first place... The driver does not care which compatible it matches against, and just uses as many interrupts as are in the dts so will happily work away without any needed changes there. @Palmer, you can take this directly as long as my fixes PR for rc3 is merged if you like, since the application path for the binding is via you anyway. I suppose I could take both too, but whatever works best for you (: Thanks, Conor. Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 2 files changed, 50 insertions(+), 31 deletions(-)