From patchwork Fri Aug 12 07:42:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 596934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA90EC00140 for ; Fri, 12 Aug 2022 07:43:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237418AbiHLHnA (ORCPT ); Fri, 12 Aug 2022 03:43:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236078AbiHLHm7 (ORCPT ); Fri, 12 Aug 2022 03:42:59 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2460BA5C7A; Fri, 12 Aug 2022 00:42:59 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 84FE75C0162; Fri, 12 Aug 2022 03:42:58 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 12 Aug 2022 03:42:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :message-id:mime-version:reply-to:sender:subject:subject:to:to; s=fm2; t=1660290178; x=1660376578; bh=sEqATm0wVZd4GFSPGrPKNfMfo m+92qSRyi/XXJHwM1s=; b=aeBVoIsHbD45G6B2CSXU/+fJbfPj6LzUteE+SGT3r urv+m1IDsRbX9YJJDBkkg9qfT/fKl8h4/Nw0c7RI9waZavC2Zcr3bS7PKMPBet5q Lc6ENhGbDyZjgilTRxYsTmsZsR1UROCiARJuuNLHcAMjtBjMshtv7mMJMoTWi+5h Xq+KgG1BDfzdtbcVMcd6El9EBfVrAPkO0dSev0HDxeUSr2rROHEGSF9V6lDNjYhT UIPHo8iO3OvaBS4oDbpKannB3q9aPFSHEQffek9wNQRSTQn8jiSD0xGrkbuI6PBp 332uFSbEt+eLEL6qNvGat3Xk9CREPQQNjCO830tYjiIdA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1660290178; x=1660376578; bh=sEqATm0wVZd4GFSPGrPKNfMfom+92qSRyi/ XXJHwM1s=; b=GY1vSeir5ajF1syvZuLHsaWDIyXnjG2u+a5LHIy+0ICG5rpB3tP Ku2pKsrtfIXv9XjXezMfRVLrgNAyO5h2iQGW8Td7z09qd/93rQ+rDM3Hr8uWmXCX N5WdXeaBkQ5iEUuZvJu/5D8DngGzFstcvKEnP7+cxSMMOLR2ralBv+IEApKCQis0 V1a2tF4SzCm2fYlvAz9iKmCvcY5rTHRksnkGPhIkXXPTEBp03Cdk4b5rlPXyqYmr /UhlOxN2zDVFh5qDHFexe2f3iyvMLXOcK87MY/XhO+VPXOuRjjHnOuhS8FG4q44M nI6jMCSu8LSNK5owaFyy/qXgoO8jM0fLVig== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdeghedguddvhecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeekveelhfejueelleetvdejvdeffeetgeelheeujeffhefgffefkeeh hffhkeekgeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 12 Aug 2022 03:42:57 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Jagan Teki , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 0/4] drm/sun4i: dsi: Support the A100/D1 controller variant Date: Fri, 12 Aug 2022 02:42:52 -0500 Message-Id: <20220812074257.58254-1-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series adds support for the digital part of the DSI controller found in the A100 and D1 SoCs (plus T7, which is not supported by mainline Linux). There are two changes to the hardware integration: 1) the module clock routes through the TCON TOP, and 2) the separate I/O domain is removed. The actual register interface appears to be the same as before. The register definitions in the D1 BSP exactly match the A64 BSP. The BSP describes this as the "40nm" DSI controller variant. There is also a "28nm" variant with a different register interface; that one is found in a different subset of SoCs (V5 and A50). A100/D1 also come with an updated DPHY, described by the BSP as a "combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI share the same pins on Port D.) Since that is a different subsystem, I am sending that as a separate series. Samuel Holland (4): dt-bindings: display: sun6i-dsi: Fix clock conditional dt-bindings: display: sun6i-dsi: Add the A100 variant drm/sun4i: dsi: Add a variant structure drm/sun4i: dsi: Add the A100 variant .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 30 +++++++--- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 58 +++++++++++++------ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 7 +++ 3 files changed, 69 insertions(+), 26 deletions(-) Reviewed-by: Jernej Skrabec