| Message ID | 20220806141059.2498226-1-vladimir.oltean@nxp.com |
|---|---|
| Headers | show |
| Series | Validate OF nodes for DSA shared ports | expand |
On Sat, 06 Aug 2022 17:10:50 +0300, Vladimir Oltean wrote: > Judging by xrs700x_phylink_get_caps(), I deduce that this switch > supports the RGMII modes on port 3, so state this phy-mode in the > example, such that users are encouraged to not rely on avoiding phylink > for this port. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > v2->v3: patch is new > > Documentation/devicetree/bindings/net/dsa/arrow,xrs700x.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Sat, 06 Aug 2022 17:10:52 +0300, Vladimir Oltean wrote: > Looking at b53_srab_phylink_get_caps() I get no indication of what PHY > modes does port 8 support, since it is implemented circularly based on > the p->mode retrieved from the device tree (and in PHY_INTERFACE_MODE_NA > it reports nothing to supported_interfaces). > > However if I look at the b53_switch_chips[] element for BCM58XX_DEVICE_ID, > I see that port 8 is the IMP port, and SRAB means the IMP port is > internal to the SoC. So use phy-mode = "internal" in the example. > > Note that this will make b53_srab_phylink_get_caps() go through the > "default" case and report PHY_INTERFACE_MODE_INTERNAL to > supported_interfaces, which is probably a good thing. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > v2->v3: patch is new > > Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Sat, 06 Aug 2022 17:10:54 +0300, Vladimir Oltean wrote: > To prevent warnings during "make dt_bindings_check" after dsa-port.yaml > will make phylink properties mandatory, add phy-mode = "internal" to the > example. > > This new property is taken straight out of the SoC dtsi at > arch/arm/boot/dts/r9a06g032.dtsi, so it seems likely that only the > example needs to be fixed, rather than DT blobs in circulation. > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > v2->v3: patch is new > > .../devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Sat, 06 Aug 2022 17:10:56 +0300, Vladimir Oltean wrote: > Modules such as net/dsa/dsa_core.ko might want to iterate through an > array of compatible strings for things such as validation (or rather, > skipping it for some potentially broken drivers). > > of_device_is_compatible() is exported, by of_device_compatible_match() > isn't. Export the latter as well, so we don't have to open-code the > iteration. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Frank Rowand <frowand.list@gmail.com> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> > --- > v1->v2: patch is new > v2->v3: none > > drivers/of/base.c | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
This is the first set of measures taken so that more drivers can be transitioned towards phylink on shared (CPU and DSA) ports some time in the future. It consists of: - expanding the DT schema for DSA and related drivers to clarify the new requirements. - introducing warnings for drivers that currently skip phylink due to incomplete DT descriptions. - introducing warning for drivers that currently skip phylink due to using platform data (search for struct dsa_chip_data). - closing the possibility for new(ish) drivers to skip phylink, by validating their DT descriptions. - making the code paths used by shared ports more evident. - preparing the code paths used by shared ports for further work to fake a link description where that is possible. More details in patch 10/10. DT binding (patches 1-6) and kernel (7-10) are in principle separable, but are submitted together since they're part of the same story. Patches 8 and 9 are DSA cleanups, and patch 7 is a dependency for patch 10. Submitting as RFC because it's RFC season, but I'd like to resend this for proper inclusion as soon as possible once the merge window closes, so ACKs/NACKs are welcome. Change log in patches. v1 at https://patchwork.kernel.org/project/netdevbpf/patch/20220723164635.1621911-1-vladimir.oltean@nxp.com/ v2 at https://patchwork.kernel.org/project/netdevbpf/patch/20220729132119.1191227-5-vladimir.oltean@nxp.com/ Cc: Rob Herring <robh+dt@kernel.org> Cc: Frank Rowand <frowand.list@gmail.com> Vladimir Oltean (10): dt-bindings: net: dsa: xrs700x: add missing CPU port phy-mode to example dt-bindings: net: dsa: hellcreek: add missing CPU port phy-mode/fixed-link to example dt-bindings: net: dsa: b53: add missing CPU port phy-mode to example dt-bindings: net: dsa: microchip: add missing CPU port phy-mode to example dt-bindings: net: dsa: rzn1-a5psw: add missing CPU port phy-mode to example dt-bindings: net: dsa: make phylink bindings required for CPU/DSA ports of: base: export of_device_compatible_match() for use in modules net: dsa: avoid dsa_port_link_{,un}register_of() calls with platform data net: dsa: rename dsa_port_link_{,un}register_of net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports .../bindings/net/dsa/arrow,xrs700x.yaml | 2 + .../devicetree/bindings/net/dsa/brcm,b53.yaml | 2 + .../devicetree/bindings/net/dsa/dsa-port.yaml | 17 ++ .../net/dsa/hirschmann,hellcreek.yaml | 6 + .../bindings/net/dsa/microchip,ksz.yaml | 4 + .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 2 + drivers/of/base.c | 1 + net/dsa/dsa2.c | 36 +++- net/dsa/dsa_priv.h | 4 +- net/dsa/port.c | 193 ++++++++++++++++-- 10 files changed, 240 insertions(+), 27 deletions(-)