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([109.76.124.168]) by smtp.gmail.com with ESMTPSA id r17-20020a5d52d1000000b0021d68a504cbsm14859618wrv.94.2022.07.26.10.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 10:07:55 -0700 (PDT) From: Conor Dooley To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou , Conor Dooley , Atul Khare , Sagar Kadam Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/2] Fix SiFive dt-schema errors Date: Tue, 26 Jul 2022 18:07:24 +0100 Message-Id: <20220726170725.3245278-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Hi all, As these are the last remaining dtbs_check warnings for the default riscv defconfig I am reviving the series. Atul has been hit by some hardware issues so has not had a chance to send an applicable version of these patches. All I have done here is rebase on linux-next, so by the time the merge window reopens it will hopefully apply.. On Atul's V2, Rob had a comment about changing the cache-sets in the patch 1/2: There is not any way to express power of 2, so you have to list values. Rather than just adding 1 more value, I would add at least a few more so we're not adding these one by one. This is for a specific cache implementation, so it can't really be *any* power of 2. Designs have some limits or physics does. /endquote I don't think that there's value in speculatively adding values to this enum especially as (I think at least) the scala for this cache IP has been released publicly: https://github.com/sifive/block-inclusivecache-sifive/blob/master/design/craft/inclusivecache/src/Parameters.scala#L32 The two compatibles in the file match only against two specific cache implemenations: the fu540's & the fu740's. I would seem to me that, it would be better to lock this to a single value per compatible since the 1024 applies to the fu540 & the new value of 2048 applies only to the fu740. I have not made that change, I simply wanted to repackage this series in a way that could be more easily applied & restart the discussion. Thanks, Conor. Atul Khare (2): dt-bindings: sifive: add cache-set value of 2048 dt-bindings: sifive: add gpio-line-names Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 ++++ Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) base-commit: 058affafc65a74cf54499fb578b66ad0b18f939b