From patchwork Fri Jul 8 14:39:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 588660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 109AEC433EF for ; Fri, 8 Jul 2022 14:39:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237631AbiGHOjY (ORCPT ); Fri, 8 Jul 2022 10:39:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237847AbiGHOjY (ORCPT ); Fri, 8 Jul 2022 10:39:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FDC41C90D; Fri, 8 Jul 2022 07:39:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657291163; x=1688827163; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VbdXyRUiSQBioCAGfM5AjkhlSoNyma51Up4CyM2gg9A=; b=eyAcQdHQUqDJ2awOzHBfOevSMV/OdkkPo2cpa/SbS60pQy3EtjP7zNEm DTZmFru2YtLGfqGQYxGrtNfyBC0MB2oSoM4rA3ijLgblQhFhqlx8vAHB0 rrFPbklCn2Owabeh0vIxDK5p0xxV40yD7c+RnaXXT4Np87WpISQn4+kw4 OjvKshfBNaEk7IJljlEXy3zzSBS1rbjjt9Hq7GacgBpBHNsQ3xOgxXMsz W2xH6GxoNIiDu9j/WGQdEg6J4vapo/whLqYmYxZxOQARnaE4xxDB3ghdG 71oOiYo1+eczuXNmK3Epu+gSNbpwHFzK39iFM+k1dTsxrwOV/1fG9p7NO g==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="171611031" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:39:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:39:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:39:20 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v5 0/4] Microchip soft ip corePWM driver Date: Fri, 8 Jul 2022 15:39:19 +0100 Message-ID: <20220708143923.1129928-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hey Uwe, all, Added some extra patches so I have a cover letter this time. You pointed out that I was overriding npwmcells in the driver and I realised that the dt & binding were not correct so I have added two simple patches to deal with that. The dts patch I will take in my tree once the binding is applied. For the maintainers entry, I mentioned before that I have several changes in-flight for it. We are late(ish) in the cycle so I doubt you'll be applying this for v5.20, but in the off chance you do - I would be happy to send it (with your Ack) alongside an i2c addition that is "deferred". In your review of v3, you had a lot of comments about the period and duty cycle calculations, so I have had another run at them. I converted the period calculation to "search" from the bottom up for the suitable prescale value. The duty cycle calculation has been fixed - the problem was exactly what I suspected in my replies to your review. I had to block the use of a 0xFF period_steps register value (which I think should be covered by the updated comment and limitation #2). Beyond that, I have rebased on -next and converted to the devm_ stuff in probe that was recently added & dropped remove() - as requested. I added locking to protect the period racing, changed the #defines and switched to returning -EINVAL when the period is locked to a value greater than that requested. Thanks, Conor. Changes from v4: - dropped some accidentally added files Conor Dooley (4): dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: fix the icicle's #pwm-cells pwm: add microchip soft ip corePWM driver MAINTAINERS: add pwm to PolarFire SoC entry .../bindings/pwm/microchip,corepwm.yaml | 4 +- MAINTAINERS | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 355 ++++++++++++++++++ 6 files changed, 371 insertions(+), 2 deletions(-) create mode 100644 drivers/pwm/pwm-microchip-core.c base-commit: 088b9c375534d905a4d337c78db3b3bfbb52c4a0