[0/3] arm64: bcmbca: add bcm6858 soc support

The initial support includes a bare-bone dts
for quad core ARM v8  with a brcm6345 uart.


Anand Gore (3):
  ARM64: dts: add dts files for bcmbca SoC bcm6858
  dt-bindings: arm64: add BCM6858 soc to binding document
  MAINTAINERS: add bcm6858 to bcmbca arch entry

 .../bindings/arm/bcm/brcm,bcmbca.yaml         |   8 ++
 MAINTAINERS                                   |   1 +
 arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
 .../boot/dts/broadcom/bcmbca/bcm6858.dtsi     | 120 ++++++++++++++++++
 .../boot/dts/broadcom/bcmbca/bcm96858.dts     |  30 +++++
 5 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
 create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts

On 2022-05-27 18:13, Anand Gore wrote:
> Add dts for ARMv8 based broadband SoC BCM6858.
> bcm6858.dtsi is the SoC description dts header
> and bcm96858.dts is a simple dts file for Broadcom
> BCM96858 Reference board that only enables the UART port.
> 
> Signed-off-by: Anand Gore <anand.gore@broadcom.com>
> 
> ---
> 
>  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
>  .../boot/dts/broadcom/bcmbca/bcm6858.dtsi     | 120 ++++++++++++++++++
>  .../boot/dts/broadcom/bcmbca/bcm96858.dts     |  30 +++++
>  3 files changed, 152 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
>  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
> 
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
> b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
> index d5f89245336c..7d98b0787b8c 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
> @@ -1,2 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
> +dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb \
> +				bcm96858.dtb
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> new file mode 100644
> index 000000000000..664b8f399d69
> --- /dev/null
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 Broadcom Ltd.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "brcm,bcm6858", "brcm,bcmbca";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		B53_0: cpu@0 {
> +			compatible = "brcm,brahma-b53";
> +			device_type = "cpu";
> +			reg = <0x0 0x0>;
> +			next-level-cache = <&L2_0>;
> +			enable-method = "psci";
> +		};
> +
> +		B53_1: cpu@1 {
> +			compatible = "brcm,brahma-b53";
> +			device_type = "cpu";
> +			reg = <0x0 0x1>;
> +			next-level-cache = <&L2_0>;
> +			enable-method = "psci";
> +		};
> +
> +		B53_2: cpu@2 {
> +			compatible = "brcm,brahma-b53";
> +			device_type = "cpu";
> +			reg = <0x0 0x2>;
> +			next-level-cache = <&L2_0>;
> +			enable-method = "psci";
> +		};
> +
> +		B53_3: cpu@3 {
> +			compatible = "brcm,brahma-b53";
> +			device_type = "cpu";
> +			reg = <0x0 0x3>;
> +			next-level-cache = <&L2_0>;
> +			enable-method = "psci";
> +		};
> +		L2_0: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	pmu: pmu {
> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&B53_0>, <&B53_1>,
> +			<&B53_2>, <&B53_3>;
> +	};
> +
> +	clocks: clocks {
> +		periph_clk:periph-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <200000000>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +		cpu_off = <1>;
> +		cpu_on = <2>;

No. Either this is PSCI 0.2 (and inventing your own function numbers
is pointless), or this isn't. Either way, this is wrong.

> +	};
> +
> +	axi@81000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0x0 0x0 0x0 0x81000000 0x0 0x4000>;
> +
> +		gic: interrupt-controller@1000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x0 0x1000 0x0 0x1000>,
> +				<0x0 0x2000 0x0 0x2000>;

GIC400 has another two regions for GICH and GICV, and a maintenance
interrupt. Please add both.

Thanks,

         M.