| Message ID | 20220218091633.9368-1-allen-kh.cheng@mediatek.com |
|---|---|
| Headers | show |
| Series | Add driver nodes for MT8192 SoC | expand |
On Fri, Feb 18, 2022 at 05:16:26PM +0800, Allen-KH Cheng wrote: > Adds H264 venc node for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 40887120fdb3..936aa788664f 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1342,6 +1342,29 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; > }; > > + vcodec_enc: vcodec@0x17020000 { The node address shouldn't have the '0x' prefix. Please drop it. > + compatible = "mediatek,mt8192-vcodec-enc"; > + reg = <0 0x17020000 0 0x2000>; > + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, > + <&iommu0 M4U_PORT_L7_VENC_REC>, > + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, > + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; Please fix indentation: iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, <&iommu0 M4U_PORT_L7_VENC_REC>, <&iommu0 M4U_PORT_L7_VENC_BSDMA>, <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; > + mediatek,scp = <&scp>; > + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; > + clocks = <&vencsys CLK_VENC_SET1_VENC>; > + clock-names = "venc-set1"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; > + }; > + > camsys: clock-controller@1a000000 { > compatible = "mediatek,mt8192-camsys"; > reg = <0 0x1a000000 0 0x1000>; > -- > 2.18.0 > >
On Fri, Feb 18, 2022 at 05:16:32PM +0800, Allen-KH Cheng wrote: > Add gce info for display nodes. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 1f1555fd18f5..df884c48669e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1226,6 +1226,9 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8192-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; As a side note, the current mmsys dt-binding, Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't define mboxes or mediatek,gce-client-reg, but looks like there's already a patch in the ML adding those: https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/ > #clock-cells = <1>; > }; > > @@ -1234,6 +1237,8 @@ > reg = <0 0x14001000 0 0x1000>; > interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; > clocks = <&mmsys CLK_MM_DISP_MUTEX0>; > + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, > + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; > }; > > smi_common: smi@14002000 { > @@ -1275,6 +1280,7 @@ > iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > }; > > ovl_2l0: ovl@14006000 { > @@ -1285,6 +1291,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > }; > > rdma0: rdma@14007000 { > @@ -1296,6 +1303,7 @@ > mediatek,larb = <&larb0>; > mediatek,rdma-fifo-size = <5120>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; > }; > > color0: color@14009000 { > @@ -1305,6 +1313,7 @@ > interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; > }; > > ccorr0: ccorr@1400a000 { > @@ -1313,6 +1322,7 @@ > interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; > }; > > aal0: aal@1400b000 { > @@ -1321,6 +1331,7 @@ > interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_AAL0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; > }; > > gamma0: gamma@1400c000 { > @@ -1330,6 +1341,7 @@ > interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; > }; > > postmask0: postmask@1400d000 { > @@ -1339,6 +1351,7 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; > }; > > dither0: dither@1400e000 { > @@ -1348,6 +1361,7 @@ > interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; > }; > > dsi0: dsi@14010000 { > @@ -1371,6 +1385,7 @@ > clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; > }; > > rdma4: rdma@14015000 { > @@ -1381,6 +1396,7 @@ > clocks = <&mmsys CLK_MM_DISP_RDMA4>; > iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > mediatek,rdma-fifo-size = <2048>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; > }; > > dpi0: dpi@14016000 { > -- > 2.18.0 > >