Message ID | 20220128120718.30545-1-yongqiang.niu@mediatek.com |
---|---|
Headers | show |
Series | add display support for mediatek SOC MT8186 | expand |
Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道: > > mt8186 routing registers is different with other Soc > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > 2 files changed, 124 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h > new file mode 100644 > index 000000000000..7de329f2d729 > --- /dev/null > +++ b/drivers/soc/mediatek/mt8186-mmsys.h > @@ -0,0 +1,113 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H > +#define __SOC_MEDIATEK_MT8186_MMSYS_H > + > +#define MT8186_MMSYS_OVL_CON 0xF04 > +#define MT8186_MMSYS_OVL0_CON_MASK 0x3 > +#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC > +#define MT8186_OVL0_GO_BLEND BIT(0) > +#define MT8186_OVL0_GO_BG BIT(1) > +#define MT8186_OVL0_2L_GO_BLEND BIT(2) > +#define MT8186_OVL0_2L_GO_BG BIT(3) > +#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C > +#define MT8186_RDMA0_SOUT_SEL_MASK 0xF > +#define MT8186_RDMA0_SOUT_TO_DSI0 (0) > +#define MT8186_RDMA0_SOUT_TO_COLOR0 (1) > +#define MT8186_RDMA0_SOUT_TO_DPI0 (2) > +#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 > +#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF > +#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) > +#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) > +#define MT8186_DISP_OVL0_MOUT_EN 0xF18 > +#define MT8186_OVL0_MOUT_EN_MASK 0xF > +#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) > +#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) > +#define MT8186_DISP_DITHER0_MOUT_EN 0xF20 > +#define MT8186_DITHER0_MOUT_EN_MASK 0xF > +#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) > +#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) > +#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) > +#define MT8186_DISP_RDMA0_SEL_IN 0xF28 > +#define MT8186_RDMA0_SEL_IN_MASK 0xF > +#define MT8186_RDMA0_FROM_OVL0 0 > +#define MT8186_RDMA0_FROM_OVL0_2L 2 > +#define MT8186_DISP_DSI0_SEL_IN 0xF30 > +#define MT8186_DSI0_SEL_IN_MASK 0xF > +#define MT8186_DSI0_FROM_RDMA0 0 > +#define MT8186_DSI0_FROM_DITHER0 1 > +#define MT8186_DSI0_FROM_RDMA1 2 > +#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C > +#define MT8186_RDMA1_MOUT_EN_MASK 0xF > +#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) > +#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) > +#define MT8186_DISP_RDMA1_SEL_IN 0xF40 > +#define MT8186_RDMA1_SEL_IN_MASK 0xF > +#define MT8186_RDMA1_FROM_OVL0 0 > +#define MT8186_RDMA1_FROM_OVL0_2L 2 > +#define MT8186_RDMA1_FROM_DITHER0 3 > +#define MT8186_DISP_DPI0_SEL_IN 0xF44 > +#define MT8186_DPI0_SEL_IN_MASK 0xF > +#define MT8186_DPI0_FROM_RDMA1 0 > +#define MT8186_DPI0_FROM_DITHER0 1 > +#define MT8186_DPI0_FROM_RDMA0 2 > + > +static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, > + MT8186_OVL0_MOUT_TO_RDMA0 > + }, > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, > + MT8186_RDMA0_FROM_OVL0 > + }, > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, > + MT8186_OVL0_GO_BLEND > + }, > + { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, > + MT8186_RDMA0_SOUT_TO_COLOR0 > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, > + MT8186_DITHER0_MOUT_TO_DSI0, > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, > + MT8186_DSI0_FROM_DITHER0 > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, > + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, > + MT8186_OVL0_2L_MOUT_TO_RDMA1 > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, > + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, > + MT8186_RDMA1_FROM_OVL0_2L > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, > + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, > + MT8186_OVL0_2L_GO_BLEND > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, > + MT8186_RDMA1_MOUT_TO_DPI0_SEL > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, > + MT8186_DPI0_FROM_RDMA1 > + }, > +}; > + > +#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 1e448f1ffefb..0da25069ffb3 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -15,6 +15,7 @@ > #include "mtk-mmsys.h" > #include "mt8167-mmsys.h" > #include "mt8183-mmsys.h" > +#include "mt8186-mmsys.h" > #include "mt8192-mmsys.h" > #include "mt8365-mmsys.h" > > @@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), > }; > > +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { > + .clk_driver = "clk-mt8186-mm", > + .routes = mmsys_mt8186_routing_table, > + .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), > +}; > + > static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > .clk_driver = "clk-mt8192-mm", > .routes = mmsys_mt8192_routing_table, > @@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { > .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data, > }, > + { > + .compatible = "mediatek,mt8186-mmsys", Add "mediatek,mt8186-mmsys" to binding document. Regards, Chun-Kuang. > + .data = &mt8186_mmsys_driver_data, > + }, > { > .compatible = "mediatek,mt8192-mmsys", > .data = &mt8192_mmsys_driver_data, > -- > 2.25.1 >
Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道: > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 ++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 6efb423ccc92..754b1be25d0d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_POSTMASK0, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > @@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { > + .main_path = mt8186_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), > + .ext_path = mt8186_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), > +}; > + > static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > .main_path = mt8192_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), > @@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8186-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8192-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-od", > @@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8186-disp-ovl", Add "mediatek,mt8186-disp-ovl" to binding document. > + .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8192-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > + { .compatible = "mediatek,mt8186-disp-ovl-2l", Ditto. > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt8192-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt8192-disp-postmask", > .data = (void *)MTK_DISP_POSTMASK }, > + { .compatible = "mediatek,mt8186-disp-postmask", Ditto. > + .data = (void *)MTK_DISP_POSTMASK}, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8167-disp-pwm", > @@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8183-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8186-dpi", Ditto. > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8183-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8186-dsi", Ditto. Regards, Chun-Kuang. > + .data = (void *)MTK_DSI }, > { } > }; > > @@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + { .compatible = "mediatek,mt8186-mmsys", > + .data = &mt8186_mmsys_driver_data}, > { .compatible = "mediatek,mt8192-mmsys", > .data = &mt8192_mmsys_driver_data}, > { } > -- > 2.25.1 >