From patchwork Fri Jan 28 11:32:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 538025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 841A7C433EF for ; Fri, 28 Jan 2022 11:32:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238177AbiA1Lcw (ORCPT ); Fri, 28 Jan 2022 06:32:52 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:19633 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235774AbiA1Lcl (ORCPT ); Fri, 28 Jan 2022 06:32:41 -0500 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 28 Jan 2022 19:32:39 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v2 0/2] refine the NFC clock framework Date: Fri, 28 Jan 2022 19:32:35 +0800 Message-ID: <20220128113237.39996-1-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Background firstly, EMMC and NAND has the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. Previously a common MMC sub clock framework is implemented and shared by EMMC and NAND, but that is coupling the EMMC and NAND, although EMMC and NAND is mutually exclusive. see the link: [https://lore.kernel.org/all/1jy23226sa.fsf@starbuckisacylon.baylibre.com/] Now we plan to abandon common mmc sub clock framework and recovery the series. Changes since v1 [2] - use clk_parent_data instead of parent_names - define a reg resource instead of sd_emmc_c_clkc [1] https://lore.kernel.org/r/20220106033130.37623-1-liang.yang@amlogic.com https://lore.kernel.org/r/20220106032504.23310-1-liang.yang@amlogic.com Liang Yang (2): mtd: rawnand: meson: discard the common MMC sub clock framework dt-bindings: nand: meson: refine Amlogic NAND controller driver .../bindings/mtd/amlogic,meson-nand.txt | 60 ------- .../bindings/mtd/amlogic,meson-nand.yaml | 70 ++++++++ drivers/mtd/nand/raw/meson_nand.c | 161 ++++++++++-------- 3 files changed, 159 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml