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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id 24sm4892127ejg.47.2022.01.17.17.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:01:51 -0800 (PST) From: Ansuel Smith To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Philipp Zabel , Ansuel Smith , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 00/14] Multiple addition and improvement to ipq8064 gcc Date: Tue, 18 Jan 2022 01:44:20 +0100 Message-Id: <20220118004434.17095-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is an attempt in making the ipq8064 SoC actually usable. Currently many feature are missing for this SoC and devs user off-the-tree patches to make it work (example patch for missing clock, patch for cpufreq driver, patch to add missing node in the dts) I notice there was some work in modernizing the gcc driver for other qcom target but this wasn't done for ipq806x. This does exactly this, we drop any parent_names stuff and we switch to the parent_data way. We also drop the pxo and cxo source clk from gcc driver and we refer to the dts for it. This also add all the missing feature for the nss cores and the cryptoengine in them. It does also introduce the required flags to make the RPM actually work and NOT reject any command. There was an attempt in declaring these clock as core clock in the dts but this ends up in no serial as the kernel makes these clock not accessible. We just want to make the kernel NOT disable them if unused nothing more. At the end we update the ipq8064 dtsi to add the pxo and cxo tag and declare them in gcc and also fix a problem with tsens probe. Ansuel Smith (14): dt-bindings: clock: Document qcom,gcc-ipq8064 binding drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table dt-bindings: clock: add ipq8064 ce5 clk define drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: reset: add ipq8064 ce5 resets drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 .../bindings/clock/qcom,gcc-ipq8064.yaml | 67 ++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +- drivers/clk/qcom/gcc-ipq806x.c | 652 +++++++++++++----- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 + 5 files changed, 567 insertions(+), 170 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml