From patchwork Fri Jan 14 09:21:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 532127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4164FC433F5 for ; Fri, 14 Jan 2022 09:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236999AbiANJVa (ORCPT ); Fri, 14 Jan 2022 04:21:30 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:34636 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234492AbiANJVa (ORCPT ); Fri, 14 Jan 2022 04:21:30 -0500 X-UUID: 6acae638e26943fbac5588e759f71ca0-20220114 X-UUID: 6acae638e26943fbac5588e759f71ca0-20220114 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 53023889; Fri, 14 Jan 2022 17:21:26 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Jan 2022 17:21:25 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Jan 2022 17:21:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 14 Jan 2022 17:21:24 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen Subject: [v9,0/3] force hsa hbp hfp packets multiple of lanenum to avoid screen shift Date: Fri, 14 Jan 2022 17:21:07 +0800 Message-ID: <20220114092110.12137-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Changes since v8: - Use mode_flags to control this limitation instead of "hs_packet_end_aligned". - Add new bit definition "MIPI_DSI_HS_PKT_END_ALIGNED" for mode_flags. Changes since v7: - Rebase to kernel 5.16 - Add tags of reviewed-by and acked-by. - Add detailed commit message for flag "hs_packet_end_aligned" in DSI common driver. Changes since v6: - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned. - Config the "hs_packet_end_aligned" in ANX7725 .attach(). Changes since v5: - Search the anx7625 compatible as flag to control dsi output aligned. Changes since v4: - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid". - Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null". Rex-BC Chen (3): drm/dsi: transfer DSI HS packets ending at the same time drm/mediatek: implement the DSI hs packets aligned drm/bridge: anx7625: config hs packets end aligned to avoid screen shift drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++- drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++ include/drm/drm_mipi_dsi.h | 2 ++ 3 files changed, 16 insertions(+), 1 deletion(-) Acked-by: AngeloGioacchino Del Regno