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Fri, 3 Sep 2021 07:00:55 +0200 Received: from maileu3.global.cadence.com (10.160.88.99) by maileu5.global.cadence.com (10.160.110.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Fri, 3 Sep 2021 07:00:55 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Fri, 3 Sep 2021 07:00:55 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 18350tQK025668; Fri, 3 Sep 2021 07:00:55 +0200 Received: (from sjakhade@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 18350sMh025667; Fri, 3 Sep 2021 07:00:54 +0200 From: Swapnil Jakhade To: , , , , , , CC: , , Subject: [PATCH 00/14] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Date: Fri, 3 Sep 2021 07:00:40 +0200 Message-ID: <20210903050054.25627-1-sjakhade@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 55a969a4-c675-479c-d7a8-08d96e97d21c X-MS-TrafficTypeDiagnostic: SN2PR07MB2735: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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PTR:unknown.Cadence.COM; CAT:NONE; SFS:(4636009)(36092001)(36840700001)(46966006)(26005)(5660300002)(110136005)(316002)(36906005)(186003)(42186006)(54906003)(508600001)(70586007)(4326008)(70206006)(8936002)(8676002)(36756003)(2906002)(47076005)(86362001)(7636003)(356005)(36860700001)(426003)(2616005)(83380400001)(1076003)(336012)(6666004)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2021 05:00:59.2579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55a969a4-c675-479c-d7a8-08d96e97d21c X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.148]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM12FT060.eop-nam12.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR07MB2735 X-Proofpoint-ORIG-GUID: X34uS_FmtTqSbBEV-p-xJFQG62k1EJPW X-Proofpoint-GUID: X34uS_FmtTqSbBEV-p-xJFQG62k1EJPW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-09-03_01,2021-09-03_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2108310000 definitions=main-2109030030 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence Sierra PHY is a multiprotocol PHY supporting different multilink PHY configurations. This patch series extends functionality of Sierra PHY driver by adding features like support for multilink multiprotocol configurations, derived reference clock etc. The changes have been validated on TI J721E platform. Swapnil Jakhade (14): phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add support for derived reference clock output .../bindings/phy/phy-cadence-sierra.yaml | 9 + drivers/phy/cadence/phy-cadence-sierra.c | 1299 +++++++++++++++-- include/dt-bindings/phy/phy-cadence.h | 5 + 3 files changed, 1224 insertions(+), 89 deletions(-)