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[RFC,v3,00/11] Linux RISC-V ACLINT Support

Message ID 20210830041729.237252-1-anup.patel@wdc.com
Headers show
Series Linux RISC-V ACLINT Support | expand

Message

Anup Patel Aug. 30, 2021, 4:17 a.m. UTC 
Most of the existing RISC-V platforms use SiFive CLINT to provide M-level
timer and IPI support whereas S-level uses SBI calls for timer and IPI
support. Also, the SiFive CLINT device is a single device providing both
timer and IPI functionality so RISC-V platforms can't partially implement
SiFive CLINT device and provide alternate mechanism for timer and IPI.

The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the
limitations of SiFive CLINT by:
1) Taking modular approach and defining timer and IPI functionality as
   separate devices so that RISC-V platforms can include only required
   devices
2) Providing dedicated MMIO device for S-level IPIs so that SBI calls
   can be avoided for IPIs in Linux RISC-V
3) Allowing multiple instances of timer and IPI devices for a
   multi-socket (or multi-die) NUMA systems
4) Being backward compatible to SiFive CLINT so that existing RISC-V
   platforms stay compliant with RISC-V ACLINT specification

Latest RISC-V ACLINT specification (to be frozen soon) can be found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

This series adds RISC-V ACLINT support and can be found in the
riscv_aclint_v3 branch at:
https://github.com/avpatel/linux

To test this series, the RISC-V ACLINT support for QEMU can be found
in the riscv_aclint_v3 branch at:
https://github.com/avpatel/qemu

Changes since v2:
 - Addresed Rob's comments on [M|S]SWI DT bindings
 - Dropped PATCH2 because it was not a required change
 - Addressed Marc's comments on ACLINT SWI driver added by PATCH7
 - Added a separate PATCH6 to update SiFive CLINT DT bindings

Changes since v1:
 - Added a new PATCH3 to treat IPIs as normal Linux IRQs for RISC-V kernel
 - New SBI IPI call based irqchip driver in PATCH3 which is only initialized
   by riscv_ipi_setup() when no Linux IRQ numbers are available for IPIs
 - Moved DT bindings patches before corresponding driver patches
 - Implemented ACLINT SWI driver as a irqchip driver in PATCH7
 - Minor nit fixes pointed by Bin Meng

Anup Patel (11):
  RISC-V: Clear SIP bit only when using SBI IPI operations
  RISC-V: Treat IPIs as normal Linux IRQs
  RISC-V: Allow marking IPIs as suitable for remote FENCEs
  RISC-V: Use IPIs for remote TLB flush when possible
  dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings
  dt-bindings: timer: Update SiFive CLINT bindings for IPI support
  irqchip: Add ACLINT software interrupt driver
  RISC-V: Select ACLINT SWI driver for virt machine
  dt-bindings: timer: Add ACLINT MTIMER bindings
  clocksource: clint: Add support for ACLINT MTIMER device
  MAINTAINERS: Add entry for RISC-V ACLINT drivers

 .../riscv,aclint-swi.yaml                     |  95 +++++++
 .../bindings/timer/riscv,aclint-mtimer.yaml   |  70 +++++
 .../bindings/timer/sifive,clint.yaml          |  20 +-
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig                            |   1 +
 arch/riscv/Kconfig.socs                       |   1 +
 arch/riscv/boot/dts/canaan/k210.dtsi          |   2 +
 .../boot/dts/microchip/microchip-mpfs.dtsi    |   2 +
 arch/riscv/include/asm/sbi.h                  |   2 +
 arch/riscv/include/asm/smp.h                  |  48 +++-
 arch/riscv/kernel/Makefile                    |   1 +
 arch/riscv/kernel/cpu-hotplug.c               |   2 +
 arch/riscv/kernel/irq.c                       |   1 +
 arch/riscv/kernel/sbi-ipi.c                   | 215 ++++++++++++++
 arch/riscv/kernel/sbi.c                       |  15 -
 arch/riscv/kernel/smp.c                       | 172 ++++++------
 arch/riscv/kernel/smpboot.c                   |   4 +-
 arch/riscv/mm/tlbflush.c                      |  91 ++++--
 drivers/clocksource/timer-clint.c             |  69 +++--
 drivers/irqchip/Kconfig                       |   9 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-riscv-aclint-swi.c        | 265 ++++++++++++++++++
 drivers/irqchip/irq-riscv-intc.c              |  55 ++--
 23 files changed, 946 insertions(+), 204 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 create mode 100644 arch/riscv/kernel/sbi-ipi.c
 create mode 100644 drivers/irqchip/irq-riscv-aclint-swi.c

Comments

Rob Herring Sept. 1, 2021, 1:29 a.m. UTC | #1 
On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote:
> The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means

> we have to create a IPI interrupt domain to use CLINT IPI functionality

> hence requiring a "interrupt-controller" and "#interrupt-cells" DT

> property in CLINT DT nodes.

> 

> Impact of this CLINT DT bindings change only affects Linux RISC-V

> NoMMU kernel and has no effect of existing M-mode runtime firmwares

> (i.e. OpenSBI).


It appears to me you should fix Linux to not need these 2 useless 
properties. I say useless because #interrupt-cells being 0 is pretty 
useless.

> 

> Signed-off-by: Anup Patel <anup.patel@wdc.com>

> ---

>  .../bindings/timer/sifive,clint.yaml          | 20 ++++++++++++++-----

>  arch/riscv/boot/dts/canaan/k210.dtsi          |  2 ++

>  .../boot/dts/microchip/microchip-mpfs.dtsi    |  2 ++

>  3 files changed, 19 insertions(+), 5 deletions(-)

> 

> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> index a35952f48742..9c8ef9f4094f 100644

> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> @@ -43,6 +43,12 @@ properties:

>  

>    interrupts-extended:

>      minItems: 1

> +    maxItems: 4095

> +

> +  "#interrupt-cells":

> +    const: 0

> +

> +  interrupt-controller: true

>  

>  additionalProperties: false

>  

> @@ -50,15 +56,19 @@ required:

>    - compatible

>    - reg

>    - interrupts-extended

> +  - interrupt-controller

> +  - "#interrupt-cells"

>  

>  examples:

>    - |

>      timer@2000000 {

>        compatible = "sifive,fu540-c000-clint", "sifive,clint0";

> -      interrupts-extended = <&cpu1intc 3 &cpu1intc 7

> -                             &cpu2intc 3 &cpu2intc 7

> -                             &cpu3intc 3 &cpu3intc 7

> -                             &cpu4intc 3 &cpu4intc 7>;

> -       reg = <0x2000000 0x10000>;

> +      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,

> +                            <&cpu2intc 3>, <&cpu2intc 7>,

> +                            <&cpu3intc 3>, <&cpu3intc 7>,

> +                            <&cpu4intc 3>, <&cpu4intc 7>;

> +      reg = <0x2000000 0x10000>;

> +      interrupt-controller;

> +      #interrupt-cells = <0>;

>      };

>  ...

> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi

> index 5e8ca8142482..67dcda1efadb 100644

> --- a/arch/riscv/boot/dts/canaan/k210.dtsi

> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi

> @@ -105,6 +105,8 @@ clint0: timer@2000000 {

>  			reg = <0x2000000 0xC000>;

>  			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7

>  					      &cpu1_intc 3 &cpu1_intc 7>;

> +			#interrupt-cells = <0>;

> +			interrupt-controller;

>  		};

>  

>  		plic0: interrupt-controller@c000000 {

> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> index b9819570a7d1..67fb41439f20 100644

> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> @@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7

>  						&cpu2_intc 3 &cpu2_intc 7

>  						&cpu3_intc 3 &cpu3_intc 7

>  						&cpu4_intc 3 &cpu4_intc 7>;

> +			#interrupt-cells = <0>;

> +			interrupt-controller;

>  		};

>  

>  		plic: interrupt-controller@c000000 {

> -- 

> 2.25.1

> 

>
Anup Patel Sept. 1, 2021, noon UTC | #2 
On Wed, Sep 1, 2021 at 6:59 AM Rob Herring <robh@kernel.org> wrote:
>

> On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote:

> > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means

> > we have to create a IPI interrupt domain to use CLINT IPI functionality

> > hence requiring a "interrupt-controller" and "#interrupt-cells" DT

> > property in CLINT DT nodes.

> >

> > Impact of this CLINT DT bindings change only affects Linux RISC-V

> > NoMMU kernel and has no effect of existing M-mode runtime firmwares

> > (i.e. OpenSBI).

>

> It appears to me you should fix Linux to not need these 2 useless

> properties. I say useless because #interrupt-cells being 0 is pretty

> useless.


Linux IRQCHIP framework only probes IRQCHIP DT nodes which
have "interrupt-controller" DT property. The "interrupt-cells" DT property
can be removed because as an interrupt controller SiFive CLINT
will only provide IPIs to arch code.

Regards,
Anup

>

> >

> > Signed-off-by: Anup Patel <anup.patel@wdc.com>

> > ---

> >  .../bindings/timer/sifive,clint.yaml          | 20 ++++++++++++++-----

> >  arch/riscv/boot/dts/canaan/k210.dtsi          |  2 ++

> >  .../boot/dts/microchip/microchip-mpfs.dtsi    |  2 ++

> >  3 files changed, 19 insertions(+), 5 deletions(-)

> >

> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> > index a35952f48742..9c8ef9f4094f 100644

> > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml

> > @@ -43,6 +43,12 @@ properties:

> >

> >    interrupts-extended:

> >      minItems: 1

> > +    maxItems: 4095

> > +

> > +  "#interrupt-cells":

> > +    const: 0

> > +

> > +  interrupt-controller: true

> >

> >  additionalProperties: false

> >

> > @@ -50,15 +56,19 @@ required:

> >    - compatible

> >    - reg

> >    - interrupts-extended

> > +  - interrupt-controller

> > +  - "#interrupt-cells"

> >

> >  examples:

> >    - |

> >      timer@2000000 {

> >        compatible = "sifive,fu540-c000-clint", "sifive,clint0";

> > -      interrupts-extended = <&cpu1intc 3 &cpu1intc 7

> > -                             &cpu2intc 3 &cpu2intc 7

> > -                             &cpu3intc 3 &cpu3intc 7

> > -                             &cpu4intc 3 &cpu4intc 7>;

> > -       reg = <0x2000000 0x10000>;

> > +      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,

> > +                            <&cpu2intc 3>, <&cpu2intc 7>,

> > +                            <&cpu3intc 3>, <&cpu3intc 7>,

> > +                            <&cpu4intc 3>, <&cpu4intc 7>;

> > +      reg = <0x2000000 0x10000>;

> > +      interrupt-controller;

> > +      #interrupt-cells = <0>;

> >      };

> >  ...

> > diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi

> > index 5e8ca8142482..67dcda1efadb 100644

> > --- a/arch/riscv/boot/dts/canaan/k210.dtsi

> > +++ b/arch/riscv/boot/dts/canaan/k210.dtsi

> > @@ -105,6 +105,8 @@ clint0: timer@2000000 {

> >                       reg = <0x2000000 0xC000>;

> >                       interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7

> >                                             &cpu1_intc 3 &cpu1_intc 7>;

> > +                     #interrupt-cells = <0>;

> > +                     interrupt-controller;

> >               };

> >

> >               plic0: interrupt-controller@c000000 {

> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> > index b9819570a7d1..67fb41439f20 100644

> > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> > @@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7

> >                                               &cpu2_intc 3 &cpu2_intc 7

> >                                               &cpu3_intc 3 &cpu3_intc 7

> >                                               &cpu4_intc 3 &cpu4_intc 7>;

> > +                     #interrupt-cells = <0>;

> > +                     interrupt-controller;

> >               };

> >

> >               plic: interrupt-controller@c000000 {

> > --

> > 2.25.1

> >

> >
Rob Herring Sept. 2, 2021, 12:18 a.m. UTC | #3 
On Wed, Sep 1, 2021 at 7:00 AM Anup Patel <anup@brainfault.org> wrote:
>

> On Wed, Sep 1, 2021 at 6:59 AM Rob Herring <robh@kernel.org> wrote:

> >

> > On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote:

> > > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means

> > > we have to create a IPI interrupt domain to use CLINT IPI functionality

> > > hence requiring a "interrupt-controller" and "#interrupt-cells" DT

> > > property in CLINT DT nodes.

> > >

> > > Impact of this CLINT DT bindings change only affects Linux RISC-V

> > > NoMMU kernel and has no effect of existing M-mode runtime firmwares

> > > (i.e. OpenSBI).

> >

> > It appears to me you should fix Linux to not need these 2 useless

> > properties. I say useless because #interrupt-cells being 0 is pretty

> > useless.

>

> Linux IRQCHIP framework only probes IRQCHIP DT nodes which

> have "interrupt-controller" DT property.


Right, I believe I wrote that... So what would it look like to fix
that? The simplest thing is just drop the check for
'interrupt-controller'. That's just a sanity check and we have other
ways to do that now (schemas). Do you need this early? You can always
implement your own initcall.


> The "interrupt-cells" DT property

> can be removed because as an interrupt controller SiFive CLINT

> will only provide IPIs to arch code.


The schema will disagree.

Rob
Anup Patel Sept. 2, 2021, 5:37 a.m. UTC | #4 
On Thu, Sep 2, 2021 at 5:48 AM Rob Herring <robh@kernel.org> wrote:
>

> On Wed, Sep 1, 2021 at 7:00 AM Anup Patel <anup@brainfault.org> wrote:

> >

> > On Wed, Sep 1, 2021 at 6:59 AM Rob Herring <robh@kernel.org> wrote:

> > >

> > > On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote:

> > > > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means

> > > > we have to create a IPI interrupt domain to use CLINT IPI functionality

> > > > hence requiring a "interrupt-controller" and "#interrupt-cells" DT

> > > > property in CLINT DT nodes.

> > > >

> > > > Impact of this CLINT DT bindings change only affects Linux RISC-V

> > > > NoMMU kernel and has no effect of existing M-mode runtime firmwares

> > > > (i.e. OpenSBI).

> > >

> > > It appears to me you should fix Linux to not need these 2 useless

> > > properties. I say useless because #interrupt-cells being 0 is pretty

> > > useless.

> >

> > Linux IRQCHIP framework only probes IRQCHIP DT nodes which

> > have "interrupt-controller" DT property.

>

> Right, I believe I wrote that... So what would it look like to fix

> that? The simplest thing is just drop the check for

> 'interrupt-controller'. That's just a sanity check and we have other

> ways to do that now (schemas). Do you need this early? You can always

> implement your own initcall.


Okay, let me first try to fix this in the driver itself. Most likely,
we will not
require changes in this DT binding.

>

>

> > The "interrupt-cells" DT property

> > can be removed because as an interrupt controller SiFive CLINT

> > will only provide IPIs to arch code.

>

> The schema will disagree.


Okay.

>

> Rob


Regards,
Anup