From patchwork Fri Aug 20 11:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chun-Jie Chen X-Patchwork-Id: 501142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16312C4320A for ; Fri, 20 Aug 2021 11:16:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF9796108F for ; Fri, 20 Aug 2021 11:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234768AbhHTLRQ (ORCPT ); Fri, 20 Aug 2021 07:17:16 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:42446 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231852AbhHTLRQ (ORCPT ); Fri, 20 Aug 2021 07:17:16 -0400 X-UUID: fb4d1c4365674fb69f4755982d7b767b-20210820 X-UUID: fb4d1c4365674fb69f4755982d7b767b-20210820 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2043987533; Fri, 20 Aug 2021 19:16:33 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Aug 2021 19:16:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 Aug 2021 19:16:32 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , Subject: [v2 00/24] Mediatek MT8195 clock support Date: Fri, 20 Aug 2021 19:14:40 +0800 Message-ID: <20210820111504.350-1-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org this patch series is based on 5.14-rc1 and depends on [1] - for makefile dependence (patches 7 ~ 19 in [1]) - for common driver dependence (patches 3 ~ 6 in [1]) changes since v1: - fix resource leak if error condition happens - refine clock name to match datasheet - remove redundant data in mux parent source - seperate clock driver based on IP architecture - change to dual licence - refine dt-binding file - remove audio clock driver (handled in [4]) - integrate vdosys0 and vdosys1 clock registration with mmsys in [2] and [3] [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=521127 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=531695 [3] https://patchwork.kernel.org/project/linux-mediatek/list/?series=519617 [4] https://patchwork.kernel.org/project/linux-mediatek/list/?series=528369 Chun-Jie Chen (24): dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock clk: mediatek: Add dt-bindings of MT8195 clocks clk: mediatek: Fix corner case of tuner_en_reg clk: mediatek: Add API for clock resource recycle clk: mediatek: Fix resource leak in mtk_clk_simple_probe clk: mediatek: Add MT8195 apmixedsys clock support clk: mediatek: Add MT8195 topckgen clock support clk: mediatek: Add MT8195 peripheral clock support clk: mediatek: Add MT8195 infrastructure clock support clk: mediatek: Add MT8195 camsys clock support clk: mediatek: Add MT8195 ccusys clock support clk: mediatek: Add MT8195 imgsys clock support clk: mediatek: Add MT8195 ipesys clock support clk: mediatek: Add MT8195 mfgcfg clock support clk: mediatek: Add MT8195 scp adsp clock support clk: mediatek: Add MT8195 vdecsys clock support clk: mediatek: Add MT8195 vdosys0 clock support clk: mediatek: Add MT8195 vdosys1 clock support clk: mediatek: Add MT8195 vencsys clock support clk: mediatek: Add MT8195 vppsys0 clock support clk: mediatek: Add MT8195 vppsys1 clock support clk: mediatek: Add MT8195 wpesys clock support clk: mediatek: Add MT8195 imp i2c wrapper clock support clk: mediatek: Add MT8195 apusys clock support .../arm/mediatek/mediatek,mt8195-clock.yaml | 254 ++++ .../mediatek/mediatek,mt8195-sys-clock.yaml | 73 + drivers/clk/mediatek/Kconfig | 8 + drivers/clk/mediatek/Makefile | 4 + drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 145 ++ drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 92 ++ drivers/clk/mediatek/clk-mt8195-cam.c | 142 ++ drivers/clk/mediatek/clk-mt8195-ccu.c | 50 + drivers/clk/mediatek/clk-mt8195-img.c | 96 ++ .../clk/mediatek/clk-mt8195-imp_iic_wrap.c | 68 + drivers/clk/mediatek/clk-mt8195-infra_ao.c | 211 +++ drivers/clk/mediatek/clk-mt8195-ipe.c | 51 + drivers/clk/mediatek/clk-mt8195-mfg.c | 47 + drivers/clk/mediatek/clk-mt8195-peri_ao.c | 62 + drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 47 + drivers/clk/mediatek/clk-mt8195-topckgen.c | 1298 +++++++++++++++++ drivers/clk/mediatek/clk-mt8195-vdec.c | 104 ++ drivers/clk/mediatek/clk-mt8195-vdo0.c | 123 ++ drivers/clk/mediatek/clk-mt8195-vdo1.c | 140 ++ drivers/clk/mediatek/clk-mt8195-venc.c | 69 + drivers/clk/mediatek/clk-mt8195-vpp0.c | 110 ++ drivers/clk/mediatek/clk-mt8195-vpp1.c | 108 ++ drivers/clk/mediatek/clk-mt8195-wpe.c | 143 ++ drivers/clk/mediatek/clk-mtk.c | 21 +- drivers/clk/mediatek/clk-mtk.h | 1 + drivers/clk/mediatek/clk-pll.c | 2 +- include/dt-bindings/clock/mt8195-clk.h | 864 +++++++++++ 27 files changed, 4330 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml create mode 100644 drivers/clk/mediatek/clk-mt8195-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt8195-apusys_pll.c create mode 100644 drivers/clk/mediatek/clk-mt8195-cam.c create mode 100644 drivers/clk/mediatek/clk-mt8195-ccu.c create mode 100644 drivers/clk/mediatek/clk-mt8195-img.c create mode 100644 drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c create mode 100644 drivers/clk/mediatek/clk-mt8195-infra_ao.c create mode 100644 drivers/clk/mediatek/clk-mt8195-ipe.c create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt8195-peri_ao.c create mode 100644 drivers/clk/mediatek/clk-mt8195-scp_adsp.c create mode 100644 drivers/clk/mediatek/clk-mt8195-topckgen.c create mode 100644 drivers/clk/mediatek/clk-mt8195-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo1.c create mode 100644 drivers/clk/mediatek/clk-mt8195-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp0.c create mode 100644 drivers/clk/mediatek/clk-mt8195-vpp1.c create mode 100644 drivers/clk/mediatek/clk-mt8195-wpe.c create mode 100644 include/dt-bindings/clock/mt8195-clk.h