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Tue, 10 Aug 2021 06:17:39 +0000 From: Jacky Bai To: shawnguo@kernel.org, robh+dt@kernel.org, abel.vesa@nxp.com, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: [PATCH v2 0/9] Add imx8ulp clock & reset driver support Date: Tue, 10 Aug 2021 14:28:11 +0800 Message-Id: <20210810062820.1062884-1-ping.bai@nxp.com> X-Mailer: git-send-email 2.26.2 X-ClientProxiedBy: SG2PR04CA0156.apcprd04.prod.outlook.com (2603:1096:4::18) To DBBPR04MB7930.eurprd04.prod.outlook.com (2603:10a6:10:1ea::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR04CA0156.apcprd04.prod.outlook.com (2603:1096:4::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.15 via Frontend Transport; Tue, 10 Aug 2021 06:17:36 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3060223d-952a-4021-021b-08d95bc68de5 X-MS-TrafficTypeDiagnostic: DB7PR04MB4636: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; 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For some of the PCC slot, As there is a SWRST control bit share the same pcc register for peripheral reset ccontrol. To simplify the case, register the pcc reset controller driver when pcc clock driver is registered. Patch 1/9 for the dt-bindings part is send out for review previously with the dts patchset: https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210607083921.2668568-1-ping.bai@nxp.com/ Shawn suggests to send out the clock driver part firstly, so this patch is included in this patchset for now. v2 changes: - remove the useless clocks & clock-names from the dt-binding doc - remove the redundant fixed clock register. Anson Huang (1): clk: imx: disable i.mx7ulp composite clock during initialization Jacky Bai (8): dt-bindings: clock: Add imx8ulp clock support clk: imx: Update the pllv4 to support imx8ulp clk: imx: Update the compsite driver to support imx8ulp clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp clk: imx: disable the pfd when set pfdv2 clock rate clk: imx: Update the pfdv2 for 8ulp specific support clk: imx: Add clock driver for imx8ulp clk: imx: Add the pcc reset controller support on imx8ulp .../bindings/clock/imx8ulp-clock.yaml | 71 +++ drivers/clk/imx/Kconfig | 7 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-composite-7ulp.c | 87 ++- drivers/clk/imx/clk-imx7ulp.c | 20 +- drivers/clk/imx/clk-imx8ulp.c | 568 ++++++++++++++++++ drivers/clk/imx/clk-pfdv2.c | 22 +- drivers/clk/imx/clk-pllv4.c | 34 +- drivers/clk/imx/clk.h | 24 +- include/dt-bindings/clock/imx8ulp-clock.h | 258 ++++++++ include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 11 files changed, 1120 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx8ulp-clock.yaml create mode 100644 drivers/clk/imx/clk-imx8ulp.c create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h