From patchwork Wed Jul 14 08:33:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 476412 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp351298jao; Wed, 14 Jul 2021 01:33:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfWvI24MAWKbvLAben1Mpb7X+JYWZaXHY81WM6Sn0CjDLZW1w6GdjQuw7ItQaXQYU/oewz X-Received: by 2002:a17:906:fa0b:: with SMTP id lo11mr10836608ejb.508.1626251620805; Wed, 14 Jul 2021 01:33:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626251620; cv=none; d=google.com; s=arc-20160816; b=szypyQiVyqTpJ1oAH1N+y0M3jClBh3fJbAwWc4SmI/r4Csptlz0F0tY0MQu/b8qVHk 6JSeWQQ/zpPjv+hzoczFlEvz8av5ke88pEJrXvv2qx6nRY9pB3b0OcOHo4MlVvUgByj2 SF+CzVLcxH6cEVZgU2iSqpvrug/tSxDHT3Br1L52yWYb9XU1R8STtUzvfrj7r3W0TwvP 56aMGg021UTU63KJFFYjejCnGXEEsqylmnqmommoZ51A87GLQYSHGncGzTvyXGS2Q/dL c47xbEs4x9D0vb0acUrnYkb6uRivKBu6MlOYpbeSJl8ux9Qzfl9FAh8/5rH7urkS3pEi tKHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=8H/NjbSTYCmJ9koYtNuq8BZ7OvXAlUKZqFY+qWvHhMM=; b=f1IX6q2ct/bV27lskaqLYpczU2F1h17H98DutIMTIlW66mirllKqfDsR3vmRBSd+kr yDo2PG15x0cnLOsDZTr0UnxhZ7000lDNmiob8drt/olqDIHpjqADt5WMzAOHx90PMxSt cxaMrX0VAsLRs3a+6fPBlsra/fc6rAVmoUnId1THvnXCD0yU+GiIDU1XuLVW5fUdw/UH id9I2ROLeFI8cAxn0/mlwcsH6kmxEnPTHFkRGynBYh1+CM1W1ZFpLvBin6MHDAHEq2D4 9W9zWuBDPPZ7dkg6tgLBsyknZGbmKPfgLKmZ3agNYA0B3CjzCKWo4ISD9S7E0OU+iN+S OTjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yr3HTmFP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qb36si2410824ejc.403.2021.07.14.01.33.40; Wed, 14 Jul 2021 01:33:40 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yr3HTmFP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238432AbhGNIg2 (ORCPT + 7 others); Wed, 14 Jul 2021 04:36:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238623AbhGNIg0 (ORCPT ); Wed, 14 Jul 2021 04:36:26 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A4BAC061764 for ; Wed, 14 Jul 2021 01:33:35 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id d12so1636074pgd.9 for ; Wed, 14 Jul 2021 01:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8H/NjbSTYCmJ9koYtNuq8BZ7OvXAlUKZqFY+qWvHhMM=; b=yr3HTmFP8ucDPkLujaUvJXMdTiQdMdqyLhKe7FifM76X+Q00JmXCzgurrkVL1u3O6p m+ZcaQYKDjYF5wUobduzgIvinTq3c9NXzGGG4jXwdojjFxuli+vpxFt2ypJyNX781vli EG5IWpqZNgjd6Gd3M0SW/WeFpJdwVRExSKVad01BrmCMavAvZSvRLnylv1TmlTW4RpDl 3YVvtywQZfGVJZ65mGax45WQR1K8+KpbMiF+5p+sD3sH5a2QmJ37DhuNk8r/j9MxD5yy UcpJegtQ+xuLukUUGOYZw0ZJLKP2pMtO3pObUsIIR5qXtYMVG28AyJ09Li5RK0IA/n3M Yvfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8H/NjbSTYCmJ9koYtNuq8BZ7OvXAlUKZqFY+qWvHhMM=; b=TcxhgVFn4WXaezyl96sNQ5VW8Sf7jEIEq5B3eXpuSPSceSGMr7SFO0rof5DW/joKCf whWP5hM5qisC9OqsRKkygyTeh5ihCwupTUfbC3AUoJff6S0BrL5uJEs7R/fwMdd7GehS BiB5w+utUl7x1tn07DRPeHXG9RKT1Vvb790/LI69Ni9zhI53C7daAYmhYjqQ4hBGXbFM lex/6jsepLusc8NPKSHDOBTFZfXNnYpuVGInjFE1lPsBaqxuHzDmp4TjAjOI1UkEPbKr tB3yhK7A/QDjntp6QLJOr3Dc7ioGSRrMcA/YXIuSBm5cqkicWcM66vSE4NnT2VjeZKUy irjQ== X-Gm-Message-State: AOAM530iPlgzXmhQdeihECPf6Xw+wOs6QiIr95i48wXlSuP5kbJzNChK 80rqgeqX0nq/xzCVdyGyKyzK X-Received: by 2002:a65:528d:: with SMTP id y13mr8570829pgp.276.1626251614838; Wed, 14 Jul 2021 01:33:34 -0700 (PDT) Received: from localhost.localdomain ([120.138.13.241]) by smtp.gmail.com with ESMTPSA id p40sm1774446pfw.79.2021.07.14.01.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jul 2021 01:33:34 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org, smohanad@codeaurora.org, bjorn.andersson@linaro.org, sallenki@codeaurora.org, skananth@codeaurora.org, vpernami@codeaurora.org, vbadigan@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v6 0/3] Add Qualcomm PCIe Endpoint driver support Date: Wed, 14 Jul 2021 14:03:13 +0530 Message-Id: <20210714083316.7835-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds support for Qualcomm PCIe Endpoint controller found in platforms like SDX55. The Endpoint controller is based on the designware core with additional Qualcomm wrappers around the core. The driver is added separately unlike other Designware based drivers that combine RC and EP in a single driver. This is done to avoid complexity and to maintain this driver autonomously. The driver has been validated with an out of tree MHI function driver on SDX55 based Telit FN980 EVB connected to x86 host machine over PCIe. Thanks, Mani Changes in v6: * Removed status property in DT and added reviewed tag from Rob * Switched to _relaxed variants as suggested by Rob Changes in v5: * Removed the DBI register settings that are not needed * Used the standard definitions available in pci_regs.h * Added defines for all the register fields * Removed the left over code from previous iteration Changes in v4: * Removed the active_config settings needed for IPA integration * Switched to writel for couple of relaxed versions that sneaked in Changes in v3: * Lot of minor cleanups to the driver patch based on review from Bjorn and Stan. * Noticeable changes are: - Got rid of _relaxed calls and used readl/writel - Got rid of separate TCSR memory region and used syscon for getting the register offsets for Perst registers - Changed the wake gpio handling logic - Added remove() callback and removed "suppress_bind_attrs" - stop_link() callback now just disables PERST IRQ * Added MMIO region and doorbell interrupt to the binding * Added logic to write MMIO physicall address to MHI base address as it is for the function driver to work Changes in v2: * Addressed the comments from Rob on bindings patch * Modified the driver as per binding change * Fixed the warnings reported by Kbuild bot * Removed the PERST# "enable_irq" call from probe() Manivannan Sadhasivam (3): dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller PCI: dwc: Add Qualcomm PCIe Endpoint controller driver MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 158 ++++ MAINTAINERS | 10 +- drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 742 ++++++++++++++++++ 5 files changed, 920 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml create mode 100644 drivers/pci/controller/dwc/pcie-qcom-ep.c -- 2.25.1