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[23.128.96.18]) by mx.google.com with ESMTP id hb19si4810005ejc.597.2021.07.08.18.31.09; Thu, 08 Jul 2021 18:31:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L0qpGINq; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230193AbhGIBdd (ORCPT + 7 others); Thu, 8 Jul 2021 21:33:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbhGIBdc (ORCPT ); Thu, 8 Jul 2021 21:33:32 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 694ECC061574 for ; Thu, 8 Jul 2021 18:30:49 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id a18so5375505ljk.6 for ; Thu, 08 Jul 2021 18:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wyP7J/Id9E/NiKqq0jzeu92fkn8P4xmDSwnVicPRwts=; b=L0qpGINqAiLCW1vDeTta9d6iA3Qhk3vsc0qpOo3yqfMdLWREhYEwaHTQ6MVA7q1hYr +AWh2YiU680qW0hGh9a7jxN6EZdNgJ8i7DiXR7kH5fMlHLxW8qEUIzF9zkHnmk7rClVq 1PlhS0v65woul6wWtwRrz+VfPIg0eu9DTn7QVUCqL6+dRngkTHLhz1T2sQgdGlVebFis F6QMElGQc6qhoGdpEFsQvh4lmbQAYoZxF72OZKia0HVnTLrGYOAidBVTm+0ROmUK7qwj Oybaoadvn99Ul0IhAfER5yEMiAr77dSb8iFZxUH1IfUDxV7PFnNf487c9ITYC3eY0DKH qMtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wyP7J/Id9E/NiKqq0jzeu92fkn8P4xmDSwnVicPRwts=; b=YHzhQy7aCp8xK72Ae7ak3MiG5i81+zfw5TctKNNtqwobx9UtbRBo+Rb6LGO0ZIXjV0 83h0CKMrnZjjYQw9rgb9zWkOiDKv95Z3UPP6Zdpi95jLVj7ADYlZ9ggfrH4fbv7G5xYu HNq+yypHIAWOmSiSujKlrAwRjGE/WiW1IPVfO+Ethbv3q0/pIzL1ffmVrlbF1Ywn//9L jJwUdx7qMtXZ2KawbGoks+5AzEA30GPA2lH8pCPiZvJdC/R1UhlHG17f6pglJ1s8C1YI bJkjKEekIk15hJ5hciytri3UTsmwXT1uBoLFhn/cUbbqvld39PnSeVb6Tm4xxV6EPFYL fN2A== X-Gm-Message-State: AOAM533ITNFb5LuSnjN2L/IDBfLqNcbdm10qZFMCjx0Au3nfPAaC8v4R wn5NM7Rwh3nn5vU9e34MstgNfg== X-Received: by 2002:a2e:a546:: with SMTP id e6mr27080250ljn.155.1625794247525; Thu, 08 Jul 2021 18:30:47 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16sm405637ljj.113.2021.07.08.18.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 18:30:47 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v2 0/7] clk: qcom: use power-domain for sm8250's clock controllers Date: Fri, 9 Jul 2021 04:30:36 +0300 Message-Id: <20210709013043.495233-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On SM8250 both the display and video clock controllers are powered up by the MMCX power domain. Handle this by linking clock controllers to the proper power domain, and using runtime power management to enable and disable the MMCX power domain. Dependencies: - https://lore.kernel.org/linux-pm/20210603093438.138705-1-ulf.hansson@linaro.org/ (merged in 5.14) - https://lore.kernel.org/linux-arm-msm/20210703005416.2668319-1-bjorn.andersson@linaro.org/ (pending) Changes since v1: - Rebase on top of Bjorn's patches, removing the need for setting performance state directly. - Move runtime PM calls from GDSC code to generic genpd code. - Always call pm_runtime_enable in the Qualcomm generic clock controller code. - Register GDSC power domains as subdomains of the domain powering the clock controller if there is one. ---------------------------------------------------------------- Dmitry Baryshkov (7): dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain dt-bindings: clock: qcom,videocc: add mmcx power domain PM: domains: Add support for runtime PM clk: qcom: gdsc: enable optional power domain support arm64: dts: qcom: sm8250: remove mmcx regulator clk: qcom: dispcc-sm8250: stop using mmcx regulator clk: qcom: videocc-sm8250: stop using mmcx regulator .../bindings/clock/qcom,dispcc-sm8x50.yaml | 7 ++++ .../devicetree/bindings/clock/qcom,videocc.yaml | 7 ++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++----- drivers/base/power/domain.c | 33 +++++++++++++++++++ drivers/clk/qcom/common.c | 37 ++++++++++++++++++---- drivers/clk/qcom/dispcc-sm8250.c | 1 - drivers/clk/qcom/gdsc.c | 5 +++ drivers/clk/qcom/videocc-sm8250.c | 4 --- include/linux/pm_domain.h | 6 ++++ 9 files changed, 91 insertions(+), 20 deletions(-)