From patchwork Thu Jun 3 22:17:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Mahadev Lad X-Patchwork-Id: 453483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B6DC47097 for ; Thu, 3 Jun 2021 22:18:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85EE161404 for ; Thu, 3 Jun 2021 22:18:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229576AbhFCWT5 (ORCPT ); Thu, 3 Jun 2021 18:19:57 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:11651 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230265AbhFCWT4 (ORCPT ); Thu, 3 Jun 2021 18:19:56 -0400 X-IronPort-AV: E=Sophos;i="5.83,246,1616425200"; d="scan'208";a="83343527" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 04 Jun 2021 07:18:09 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D3E93410B534; Fri, 4 Jun 2021 07:18:05 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Michael Turquette , Stephen Boyd , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Jiri Slaby , Philipp Zabel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org Cc: Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 00/12] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Date: Thu, 3 Jun 2021 23:17:46 +0100 Message-Id: <20210603221758.10305-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi All, This patch series adds initial support for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK. Initial patches enables minimal peripherals on Renesas RZ/G2L SMARC EVK and booted via initramfs. * Documentation for RZ/G2{L,LC,UL} SoC variants * SoC identification support * CPG core support * Minimal SoC DTSi * Minimal DTS for SMARC EVK Changes for v2: * Included type-2 RZ/G2Ul SoC in binding doc * Added single entry for SMARC EVK "renesas,smarc-evk" * Renamed ARCH_R9A07G044L to ARCH_R9A07G044 and dropped ARCH_R9A07G044LC config * Dropped SoC identification changes will post them as separate patch. * Updated comment in sh-sci.c * Binding documentation patch for serial driver has been accepted so dropped the patch from this series * Incorporated changes requested by Geert for CPG core * Fixed dtbs_check errors * Dropped 'clock-names'/'clocks'/'power-domains'/'resets' properties from GIC node and will include them in a separate patch along with arm,gic-v3.yaml binding updates * Included ACK's from Rob Patches are based on top of [1] master branch. [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/ Cheers, Prabhakar Biju Das (1): serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar (11): dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants dt-bindings: arm: renesas: Document SMARC EVK soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's arm64: defconfig: Enable ARCH_R9A07G044 clk: renesas: Define RZ/G2L CPG Clock Definitions dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver clk: renesas: Add CPG core wrapper for RZ/G2L SoC clk: renesas: Add support for R9A07G044 SoC arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK .../devicetree/bindings/arm/renesas.yaml | 18 + .../bindings/clock/renesas,rzg2l-cpg.yaml | 80 ++ arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 119 +++ arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 + .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 + arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 9 + drivers/clk/renesas/Makefile | 2 + drivers/clk/renesas/r9a07g044-cpg.c | 372 +++++++ drivers/clk/renesas/renesas-rzg2l-cpg.c | 979 ++++++++++++++++++ drivers/clk/renesas/renesas-rzg2l-cpg.h | 217 ++++ drivers/soc/renesas/Kconfig | 5 + drivers/tty/serial/sh-sci.c | 12 +- drivers/tty/serial/sh-sci.h | 1 + include/dt-bindings/clock/r9a07g044-cpg.h | 89 ++ 17 files changed, 1978 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.c create mode 100644 drivers/clk/renesas/renesas-rzg2l-cpg.h create mode 100644 include/dt-bindings/clock/r9a07g044-cpg.h