| Message ID | 20210508070930.5290-1-sergio.paracuellos@gmail.com |
|---|---|
| Headers | show |
| Series | phy: ralink: mt7621-pci-phy: some improvements | expand |
On 08-05-21, 09:09, Sergio Paracuellos wrote: > Hi all, > > This series contains some improvements in the pci phy driver > for MT7621 SoCs. > > MT7621 SoC clock driver has already mainlined in > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > Because of this we can update schema documentation and device tree > to add related clock entries and avoid custom architecture code > in favour of using the clock kernel framework to retrieve clock > frequency needed to properly configure the PCIe related Phys. > > After this changes there is no problem to properly enable this > driver for COMPILE_TEST. > > Configuration has also modified from 'tristate' to 'bool' depending > on PCI_MT7621 which seems to have more sense. Applied 2-6, thanks -- ~Vinod
On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul@kernel.org> wrote: > > On 08-05-21, 09:09, Sergio Paracuellos wrote: > > Hi all, > > > > This series contains some improvements in the pci phy driver > > for MT7621 SoCs. > > > > MT7621 SoC clock driver has already mainlined in > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > > > Because of this we can update schema documentation and device tree > > to add related clock entries and avoid custom architecture code > > in favour of using the clock kernel framework to retrieve clock > > frequency needed to properly configure the PCIe related Phys. > > > > After this changes there is no problem to properly enable this > > driver for COMPILE_TEST. > > > > Configuration has also modified from 'tristate' to 'bool' depending > > on PCI_MT7621 which seems to have more sense. > > Applied 2-6, thanks Thanks, Vinod. Greg, can you take patch 1 through your tree? Best regards, Sergio Paracuellos > > -- > ~Vinod
On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote: > On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul@kernel.org> wrote: > > > > On 08-05-21, 09:09, Sergio Paracuellos wrote: > > > Hi all, > > > > > > This series contains some improvements in the pci phy driver > > > for MT7621 SoCs. > > > > > > MT7621 SoC clock driver has already mainlined in > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > > > > > Because of this we can update schema documentation and device tree > > > to add related clock entries and avoid custom architecture code > > > in favour of using the clock kernel framework to retrieve clock > > > frequency needed to properly configure the PCIe related Phys. > > > > > > After this changes there is no problem to properly enable this > > > driver for COMPILE_TEST. > > > > > > Configuration has also modified from 'tristate' to 'bool' depending > > > on PCI_MT7621 which seems to have more sense. > > > > Applied 2-6, thanks > > Thanks, Vinod. > > Greg, can you take patch 1 through your tree? Sure, can you resend it? thanks, greg k-h
On Fri, May 14, 2021 at 1:22 PM Greg KH <gregkh@linuxfoundation.org> wrote: > > On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote: > > On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul@kernel.org> wrote: > > > > > > On 08-05-21, 09:09, Sergio Paracuellos wrote: > > > > Hi all, > > > > > > > > This series contains some improvements in the pci phy driver > > > > for MT7621 SoCs. > > > > > > > > MT7621 SoC clock driver has already mainlined in > > > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' > > > > > > > > Because of this we can update schema documentation and device tree > > > > to add related clock entries and avoid custom architecture code > > > > in favour of using the clock kernel framework to retrieve clock > > > > frequency needed to properly configure the PCIe related Phys. > > > > > > > > After this changes there is no problem to properly enable this > > > > driver for COMPILE_TEST. > > > > > > > > Configuration has also modified from 'tristate' to 'bool' depending > > > > on PCI_MT7621 which seems to have more sense. > > > > > > Applied 2-6, thanks > > > > Thanks, Vinod. > > > > Greg, can you take patch 1 through your tree? > > Sure, can you resend it? Thanks, I have just resent it. > > thanks, > > greg k-h Best regards, Sergio Paracuellos
Hi all, This series contains some improvements in the pci phy driver for MT7621 SoCs. MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Because of this we can update schema documentation and device tree to add related clock entries and avoid custom architecture code in favour of using the clock kernel framework to retrieve clock frequency needed to properly configure the PCIe related Phys. After this changes there is no problem to properly enable this driver for COMPILE_TEST. Configuration has also modified from 'tristate' to 'bool' depending on PCI_MT7621 which seems to have more sense. Thanks in advance for your time. Changes in v2 resed: - Forgot to send the series to devicetree list. Sorry for inconvenience. Changes in v2: - Drop 'clock-names' property from device tree and binding doc sice only one clock is needed. - Update driver code to don't get clock name as identifier for the clock but just use NULL. - Add patch to fix a COMPILE_TEST reported issue because of the way printing of a pointer was being done. This patch was already send by its own[0] but to have all of this applied together I prefer to include it here. Best regards, Sergio Paracuellos [0]: http://lists.infradead.org/pipermail/linux-phy/2021-May/000395.html Sergio Paracuellos (6): staging: mt7621-dts: use clock in pci phy nodes dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries phy: ralink: phy-mt7621-pci: use kernel clock APIS phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' phy: ralink: phy-mt7621-pci: properly print pointer address .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 5 +++ drivers/phy/ralink/Kconfig | 4 +- drivers/phy/ralink/phy-mt7621-pci.c | 37 +++++++++++-------- drivers/staging/mt7621-dts/mt7621.dtsi | 2 + 4 files changed, 31 insertions(+), 17 deletions(-)