From patchwork Wed Mar 10 15:45:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 396729 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp483295jai; Wed, 10 Mar 2021 07:47:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJxx1hBHoxZQTvVEBzF0hgRKUwPREE56Q8KXcKMvyRCdMfjtoX6j0u6jIxc4WyJWFHdGxxq5 X-Received: by 2002:a17:906:8904:: with SMTP id fr4mr4467138ejc.136.1615391234736; Wed, 10 Mar 2021 07:47:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615391234; cv=none; d=google.com; s=arc-20160816; b=NUROgSrQwE8/WpLjuHWe/M9Rx4CVFB4FGMawhkGwUBVAD/60ZcRezv1bH59HVGB6rh E6W/K1fufTNRR3SxeYUlq3ZaAbRHSCgpT2BlOTYipwU6QDz1OwdBT1CHQFpWJFpR6ann LhScZV/uisxgq7P4bW09iW6qfz9FNrtiwIBj/TwfFU9jxDQCWWdPj8ifiJxy+E2zP3xZ 6Xk4aMYmtXUvYAs2orLHdanGEk+7Mbc6C12g4Bq1/g+t6V+p1e2LmJYJLUQfiUKQzPxg CpmAUoqiBgI/pHq43NHxHNpIHez5nafOS5rkdbLIsIhYngRMyZXaxENvbOO74rPzWUIt 44yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=AUn7XpCLIngAp4n26qKR/3PFFYMJbQoYcvX98ciR6gI=; b=K9OmgCYAgWiaYfmpO/SusReJsbN8+Rx797Cst+jLpMAEmKY4u+F3D6gGWJWSSRoutN 6R2sL2gvizqCl5E/y9g8gE3efQJWVAa1A8nfMsQQwM3LCz/AKRL/CKVp+sameDmnmCnB BjQqIhSN+7nZ9ci6NMvdrjs3ArBe48sjgMXjhYZnj6dJ8Za9YIypayfXdAoa2PT46EjF TcBZh4rdQLl0Ibdd2E0RrDz3JEr3LsC3Mmh3jkd6LS7JVpwvxHvYq2Ly+c1hQ1inOSZW BWVHLG4u8L7tWQfszpYEqkMr1Of3wUdDJyDEoh1x+Crf40AP6NzcE5t0i9ip0IHO+gnI +awA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rqtHkgX5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t3si4576077ejy.142.2021.03.10.07.47.14; Wed, 10 Mar 2021 07:47:14 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rqtHkgX5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233233AbhCJPql (ORCPT + 6 others); Wed, 10 Mar 2021 10:46:41 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:47654 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232818AbhCJPqN (ORCPT ); Wed, 10 Mar 2021 10:46:13 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12AFk6CN067600; Wed, 10 Mar 2021 09:46:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1615391166; bh=AUn7XpCLIngAp4n26qKR/3PFFYMJbQoYcvX98ciR6gI=; h=From:To:CC:Subject:Date; b=rqtHkgX5OhrDx6BZ2cqWuHo6NV5PQoMaemvR3lck9KwOi7esikm2d3C7QiYlI/qYT X/zSETkHjSi67TeNUJFOkj201yx37st8uEAfuGV9x1AujESuuxRwzDuYFNHM7wfMG7 xfoR5oVCkGMoR/PcmycL/Gl5/Kly0roWaYvHnvlE= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12AFk6WN087462 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Mar 2021 09:46:06 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 10 Mar 2021 09:46:05 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 10 Mar 2021 09:46:05 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12AFk2KO066370; Wed, 10 Mar 2021 09:46:02 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel , Swapnil Jakhade CC: , , Lokesh Vutla Subject: [PATCH v6 00/13] PHY: Add support in Sierra to use external clock Date: Wed, 10 Mar 2021 21:15:45 +0530 Message-ID: <20210310154558.32078-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Patch series adds support in Sierra driver to use external clock. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [2] v3 of the patch series can be found @ [3] v5 of the patch series can be found @ [5] v6 of the patch series can be found @ [6] Changes from v5: 1) Added Rob's Reviewed-by for the DT binding 2) Fixed another error handling case pointed out by Swapnil 3) Fixed few checkpatch errors. Changes from v4: 1) Fixed couple of error handling cases 2) Added reviewed by from Philipp Zabel 3) Fixed couple of patch commit subjects to be uniform with other patches. Changes from v3: 1) Instead of adding separate subnodes for each clock, just add #clock-cells in Sierra SERDES nodes and model the clocks. This is in alignment with Rob's comment for a different series [4] 2) Removed device tree changes from the series. Changes from v2: 1) Add depends on COMMON_CLK in Sierra 2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate patch 3) Disable clocks in Sierra driver remove Changes from v1: 1) Remove the part that prevents configuration if the SERDES is already configured and focus only on using external clock and the associated cleanups 2) Change patch ordering 3) Use exclusive reset control APIs 4) Fix error handling code 5) Include DT patches in this series (I can send this separately to DT MAINTAINER once the driver patches are merged) [1] -> http://lore.kernel.org/r/20201103035556.21260-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20201222070520.28132-1-kishon@ti.com [3] -> http://lore.kernel.org/r/20201224111627.32590-1-kishon@ti.com [4] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org [5] -> https://lore.kernel.org/r/20210304044122.15166-1-kishon@ti.com [6] -> https://lore.kernel.org/r/20210308050732.7140-1-kishon@ti.com Kishon Vijay Abraham I (13): phy: cadence: Sierra: Fix PHY power_on sequence phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function phy: cadence: cadence-sierra: Explicitly request exclusive reset control phy: cadence-torrent: Use a common header file for Cadence SERDES phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks .../bindings/phy/phy-cadence-sierra.yaml | 17 +- drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 419 ++++++++++++++++-- drivers/phy/cadence/phy-cadence-torrent.c | 2 +- drivers/phy/ti/phy-j721e-wiz.c | 21 +- include/dt-bindings/phy/phy-cadence-torrent.h | 15 - include/dt-bindings/phy/phy-cadence.h | 20 + 7 files changed, 428 insertions(+), 67 deletions(-) delete mode 100644 include/dt-bindings/phy/phy-cadence-torrent.h create mode 100644 include/dt-bindings/phy/phy-cadence.h -- 2.17.1