From patchwork Wed Jan 27 07:08:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371481 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp4924jam; Tue, 26 Jan 2021 23:13:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkl3bo3vz9kJ+QYmKh8eBLX/xKgMrr+tarWsZMZR5Ae6599RqWsGDewkT3ZYDVh9CxBBJX X-Received: by 2002:a17:906:1958:: with SMTP id b24mr5777247eje.263.1611731610885; Tue, 26 Jan 2021 23:13:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611731610; cv=none; d=google.com; s=arc-20160816; b=vb6YDIkw6KsPeyPBrEkkMyVUYg3oVmw9dgoSRia4QLIviMXOA0Rib1CmNEI9zkh6TL EoxnuID5L3/MZg4OpTCgQ6OaifIRv8FOagnhEVsZmjEJ91XbZxBAYxk1RB0zC+dJdgeU NaqN6uDebHMqz3za2cJh4rYptAEdIPXjQxI/aqLJ1ZUqOqAioYr12qLl0tudwjJZ4ZFP fapuKnr+5bpHP00q5UINUtw3DnZEjroM0JrKybmi7ya5cAzF+db9fcOAYvbHZSx+WV5s mwFH9cVbzkT6z8CnPDh/Q0Ns7d5fPhEjrNCrMYC6T1Ma0oZUvmtVIidZsLSyQDQE/Stk i/Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=TDAeASu5pS0dMd+nGX8nIhIRqSFeDWJuwBTZsItkJZ0=; b=M2GHmNG+6JMwwCK9QJDY/zK9EZIVRmr5m1EXtfJ1xXcg6uTcPrYlSOaA4xmOKU8PeY 10/I22hLL3t0WFd0wk2NMG5r75t75cfzQnXoE8oW+5mQCoWLUsXHkkAbKjU5hgVUjWPj t48CHGW8LBSUqq4TJyC7UWAuLX5KbBPyeCToUCH4wHzG/f86qjv6+lfbPqbNgAZG+jVW hMcafoqAOOs4cG9p4Ml+sHt0YspU5SVJqQ7qdE90jz5xf7VUVsYbxLIjMQVYU26grn9V /Ymue491qdWZulm+JDr0l2pIFKiV0nFKrwP+t0krLCwCvHKPiKDd5BriciAVByTiZJIa 83+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="J/VLsnQv"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ga16si463787ejc.412.2021.01.26.23.13.30; Tue, 26 Jan 2021 23:13:30 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="J/VLsnQv"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232840AbhA0HMa (ORCPT + 6 others); Wed, 27 Jan 2021 02:12:30 -0500 Received: from mail.kernel.org ([198.145.29.99]:45486 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232372AbhA0HJB (ORCPT ); Wed, 27 Jan 2021 02:09:01 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9EACC20724; Wed, 27 Jan 2021 07:08:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611731300; bh=h6gEAcgIWOUdRrfszLr2SUwM5JmAGj8Uwzmk+TImk/k=; h=From:To:Cc:Subject:Date:From; b=J/VLsnQv2NxTJ/b7PYohkQlIkhAqXg+NGTBKP0FG/wwPjicHsHmSemC7vVBwqxBaG gdoacmVpQeDtFBLdv8nPQo2ap51vLUYrjw3mISwtbxHP4iVwbyVnLa3RNYc9QivaIw iKc0TixKK8BzLZs0qwSNAMUYc+jxYOn13Bd8tUljr1RQAFGyIgVhhtpZtfcTfMyXva 51Y+TPTa+ItLarti5utcVWAnQvVsfESDNsYJ87SdDthm/B7UuhTIVVLPFa0bIH/7uq 9mF8UYA7j6iCIXGmmC4zayO7R6Sof91h9WI1ppJSteB6Yl81Kmi1Rs06SX0qFG0f6L xwMwBlWsa9kzg== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 0/5] Add clock drivers for SM8350 Date: Wed, 27 Jan 2021 12:38:06 +0530 Message-Id: <20210127070811.152690-1-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds gcc clock controller drivers for the controller found in SM8350 SoC Changes in v5: - Add r-b from AngeloGioacchino and Bjorn - Removed unused clock indices - Initialize variable before use in regmap read Changes in v4: - Add Ack from Rob on binding - modularize alpha_pll_trion_set_rate() Changes in v3: - Drop rpmh clk patches applied - Add a new patch to replace regval with val as suggested by Stephen - Fix comments for new Lucid 5LPE PLL: sort new defines by BIT numbers, fix comments, use alpha_pll_check_rate_margin(), rework clk_lucid_5lpe_pll_postdiv_set_rate() logic - Add power domains and optional clocks in bindings - Fix comments for gcc sm8350 driver: clean includes used, use only .fw_name for clocks defined in DT, use floor ops for sdcc clocks, remove critical clocks and enable them in probe, add comments for clks using BRANCH_HALT_SKIP and BRANCH_HALT_DELAY Changes in v2: - Add r-b from Bjorn - Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk Vinod Koul (3): clk: qcom: clk-alpha-pll: replace regval with val clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate() dt-bindings: clock: Add SM8350 GCC clock bindings Vivek Aknurwar (2): clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL clk: qcom: gcc: Add clock driver for SM8350 .../bindings/clock/qcom,gcc-sm8350.yaml | 96 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 209 +- drivers/clk/qcom/clk-alpha-pll.h | 4 + drivers/clk/qcom/gcc-sm8350.c | 3790 +++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8350.h | 254 ++ 7 files changed, 4346 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml create mode 100644 drivers/clk/qcom/gcc-sm8350.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h -- 2.26.2