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[23.128.96.18]) by mx.google.com with ESMTP id z5si1783932ejj.220.2021.01.21.04.41.33; Thu, 21 Jan 2021 04:41:33 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eWz40E4P; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731408AbhAUMkf (ORCPT + 6 others); Thu, 21 Jan 2021 07:40:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730552AbhAUMkN (ORCPT ); Thu, 21 Jan 2021 07:40:13 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C525C061757 for ; Thu, 21 Jan 2021 04:39:32 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id a12so1587237wrv.8 for ; Thu, 21 Jan 2021 04:39:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b3l0OetoC6tw2Q4vXg0OJU58lOnJngSuhcgcpV0j+8A=; b=eWz40E4PQwAOppqBXOwKvt7Q0dVqHUMh5fqoJvuQDA3+kHfzRAM63s2hCG8pfXf/KX t1YLSGF55pBNR2O9qMkU8XNhlJEEPEFxSPI+KSsuahcO6/fMwqXvmQIo6j1dfavCmDdj 2B4/qfVkLa0wBIQM3C7X6KgbYGm6oqE9MOBt17J/hCH9OvzxW2nN3/Fafr9nNHhw1pKd KvmOhkIHRvFkOP99nRyu5JXBGxSs8J9RFK95nw/VPMXO4yliQAc11MxeVpIy76ZiUVm2 hY98zO+6QyqZygvqDXOilArvpDWBw4lbh2dFhPuehwvVGwJAKaiui4K6V79Pg/DqOpRc a7+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b3l0OetoC6tw2Q4vXg0OJU58lOnJngSuhcgcpV0j+8A=; b=qvayMY7m4gmFMgPWQnjHgnvyGjGZD4vZH9xQ6c5Se8gT409sNjLGk1TVCPQbQC0WCa w32SnEku29AndCqQ4El4ZPixjoZoz5clB5GSHBNW5k7iv3Fm7504UiiLbdO2sgoar2/8 9viSYzJpKgRfv/icG9QR+1c3KS4XcQfKcdxujaTTSJHsfaUULIf9PW6lCyq5zo9T6qbO QrhUgw1nFNZtjnr6O75oWENVPdMkV6kK2zi1jlfeNTpkc2IumETd9Jb7jmlTECkNcayt EFEDlESWrAk7dxiXMYMNMJDZEUgE0zvJ+tsd1yONvHtvsjCACCfgRlqzEI3L6n01/MfK KMkw== X-Gm-Message-State: AOAM531PDxcQzFxaW7wM481f9+sRmMOkmRhdVDPZHshjS1KI/kY71tdD LE4RkUgtEWRTNar4RLydBMEuKA== X-Received: by 2002:adf:d20b:: with SMTP id j11mr13720018wrh.318.1611232771208; Thu, 21 Jan 2021 04:39:31 -0800 (PST) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id p18sm7979248wmc.31.2021.01.21.04.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 04:39:30 -0800 (PST) From: Jean-Philippe Brucker To: joro@8bytes.org, will@kernel.org Cc: lorenzo.pieralisi@arm.com, robh+dt@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, robin.murphy@arm.com, Jonathan.Cameron@huawei.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-accelerators@lists.ozlabs.org, baolu.lu@linux.intel.com, jacob.jun.pan@linux.intel.com, kevin.tian@intel.com, vdumpa@nvidia.com, zhangfei.gao@linaro.org, shameerali.kolothum.thodi@huawei.com, vivek.gautam@arm.com, Jean-Philippe Brucker Subject: [PATCH v10 00/10] iommu: I/O page faults for SMMUv3 Date: Thu, 21 Jan 2021 13:36:14 +0100 Message-Id: <20210121123623.2060416-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add stall support to the SMMUv3, along with a common I/O Page Fault handler. Changes since v9 [1]: * Style changes suggested by Jonathan * Fixes to patch 10 pointed out by Robin * In patch 10, don't register the mm fault handler when enabling IOMMU_DEV_FEAT_IOPF, because that feature only indicates that a device driver wants to use PRI or stall. After enabling it, drivers may register their own IOPF handler (see discussion on v9 patch 03). Instead register the mm handler when enabling IOMMU_DEV_FEAT_SVA. [1] https://lore.kernel.org/linux-iommu/20210108145217.2254447-1-jean-philippe@linaro.org/ Jean-Philippe Brucker (10): iommu: Fix comment for struct iommu_fwspec iommu/arm-smmu-v3: Use device properties for pasid-num-bits iommu: Separate IOMMU_DEV_FEAT_IOPF from IOMMU_DEV_FEAT_SVA iommu/vt-d: Support IOMMU_DEV_FEAT_IOPF uacce: Enable IOMMU_DEV_FEAT_IOPF iommu: Add a page fault handler iommu/arm-smmu-v3: Maintain a SID->device structure dt-bindings: document stall property for IOMMU masters ACPI/IORT: Enable stall support for platform devices iommu/arm-smmu-v3: Add stall support for platform devices drivers/iommu/Makefile | 1 + .../devicetree/bindings/iommu/iommu.txt | 18 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 56 ++- drivers/iommu/iommu-sva-lib.h | 53 ++ include/linux/iommu.h | 26 +- drivers/acpi/arm64/iort.c | 15 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 59 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 347 +++++++++++-- drivers/iommu/intel/iommu.c | 11 +- drivers/iommu/io-pgfault.c | 461 ++++++++++++++++++ drivers/iommu/of_iommu.c | 5 - drivers/misc/uacce/uacce.c | 39 +- 12 files changed, 1018 insertions(+), 73 deletions(-) create mode 100644 drivers/iommu/io-pgfault.c -- 2.30.0 Acked-by: Jonathan Cameron Reviewed-by: Lu Baolu